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| 19-4572; Rev 0; 4/09 Crimzon(R) Infrared Microcontrollers ZLF645 Series Flash MCUs with Learning Amplification Product Specification Maxim Integrated Products Inc. 120 San Gabriel Drive, Sunnyvale CA 94086 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale, CA 94086 United States 408-737-7600 www.maxim-ic.com Copyright (c) 2009 Maxim Integrated Products Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. Maxim retains the right to make change s to its products or specifications to improve performance, reliability or manufacturability. All information in this document, includin g descriptions of f eatures, functio ns, per formance, technical specifications and avai lability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Maxim for its use. F urthermore, the information contained her ein does not c onvey to the pur chaser of micr oelectronic devices any license under the patent right of any manufacturer. Maxim is a registered trademark of Maxim Integrated Products, Inc. All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered tr ademarks mentioned he rein are th e property of th eir respective holders. Z8 is a registered trademark of Zilog, Inc. Crimzon is a registered trademark of Universal Electronics Inc. 19-4572; Rev 0; 4/09 ZLF645 Series Flash MCUs Product Specification iii Revision History Each instance in the revision history table reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate links given in the table below. Date Version Description Updated formula in Flash Controller section. Updated VLVD in Table 80 and VFLPE in Table 82 in Electrical Characteristics section. Updated Table 56 through Table 59 in Timers section. Added Flash Programming through the ICP Interface in ICP Interface section. Added Using the Watchdog Timer As a Stop Mode Recovery Source in Reset and Power Management section. Updated Flash Frequency High and Low Byte Registers section and Table 83. Updated Port 1 pins in Figure 1. Updated Enabling The Flash Byte Programming Interface section. Page Number 67 165, 170 119 61 142 79, 172 4 82 December 08 2008 April 2008 07 April 2008 06 Deleted "Design Info" subsection and all of its associated All text. Updated Flash Memory Overview section; updated 67, 68 Figure 19. Updated Flash Frequency High and Low Byte Registers 79 section. Updated Icc and Icc1 in Table 80. 165 Updated notes in Table 5 and Table 6. 9, 10 Removed "Preliminary" and "Precharacterization Product" All notice. Added 20-pin QFN package to Pin Description, Table 3, 5, 6, 7, Table 4, Packaging, Table 87, and Part Number 176, 184, 186 Description. 85 Change P31 to P32 at the beginning of Universal Asynchronous Receiver/Transmitter. Updated Flash Code Protection Against External Access and Flash Frequency High and Low Byte Registers. Chapter Reset and Power Management: Updated Table 68. 73, 79 142 January 2008 January 2008 05 04 19-4572; Rev 0; 4/09 Revision History ZLF645 Series Flash MCUs Product Specification iv Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0/1 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 3 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 4 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Program/Constant Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Pointer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 2 4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 18 18 20 21 22 23 28 28 28 30 31 32 33 34 35 36 37 39 40 41 41 42 42 45 45 48 48 19-4572; Rev 0; 4/09able of ContentsTable able of Table Table of Contents ZLF645 Series Flash MCUs Product Specification v Register File Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ICP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling ICP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State of ZLF645 in ICP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Flash Accesses Through the ICP . . . . . . . . . . . . . . . . . . . . . . . . . ICP Interface Logic Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICP Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICP Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICP Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICP Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICP In-Circuit Programming Commands . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Programming through the ICP Interface . . . . . . . . . . . . . . . . . . . . . . Differences Between CPU Based and ICP Based Flash Programming/ Erase Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using ICP Commands for Flash Programming/Read Operations . . . . . In-Circuit Programming Control Register Definitions . . . . . . . . . . . . . . . . . . ICP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exiting ICP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Information Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Executing Flash Memory Accesses Through the Flash Controller . . . . Flash Code Protection Against External Access . . . . . . . . . . . . . . . . . . Flash Code Protection Against Accidental Program and Erasure . . . . . Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . Flash Controller Functions Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 53 53 53 54 54 54 55 55 56 57 61 61 61 64 64 65 66 66 67 67 68 69 69 73 73 74 74 75 75 75 77 77 78 79 80 Flash Byte Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 19-4572; Rev 0; 4/09able of ContentsTable able of Table Table of Contents ZLF645 Series Flash MCUs Product Specification vi Enabling The Flash Byte Programming Interface . . . . . . . . . . . . . . . . . . . . 82 Flash Byte Programming Interface Flash Access Restrictions . . . . . . . . . . 82 Infrared Learning Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitting Data Using Polled Method . . . . . . . . . . . . . . . . . . . . . . . . Transmitting Data Using Interrupt-Driven Method . . . . . . . . . . . . . . . . . Receiving Data Using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . Receiving Data Using the Interrupt-Driven Method . . . . . . . . . . . . . . . . UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Receive Data Register/UART Transmit Data Register . . . . . . . . . . . UART Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Baud Rate Generator Constant Register . . . . . . . . . . . . . . . . . . . . . 85 86 86 87 87 88 89 89 90 93 95 95 96 97 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 T8 TRANSMIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 T8 DEMODULATION Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 T16 TRANSMIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 T16 DEMODULATION Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 PING-PONG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Counter/Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Timer 8 Capture High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Timer 8 Capture Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Timer 16 Capture High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Timer 16 Capture Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Counter/Timer 16 High Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . 116 Counter/Timer 16 Low Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . 117 Counter/Timer 8 High Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Counter/Timer 8 Low Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Counter/Timer 8 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 T8 and T16 Common Functions Register . . . . . . . . . . . . . . . . . . . . . . 121 Counter/Timer 16 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Timer 8/Timer 16 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 19-4572; Rev 0; 4/09able of ContentsTable able of Table Table of Contents ZLF645 Series Flash MCUs Product Specification vii Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal 1 Oscillator Pin (XTAL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal 2 Oscillator Pin (XTAL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Clock Signals (SCLK and TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . Reset and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Brownout Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Watchdog Timer As a Stop Mode Recovery Source . . . . . . Reset/Stop Mode Recovery Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode Recovery Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode Recovery Event Sources . . . . . . . . . . . . . . . . . . . . . . . . . . SMR Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMR1 Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMR2 Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMR3 Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode Recovery Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z8 LXMC CPU Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 130 131 133 134 135 135 135 137 139 139 139 140 141 141 142 143 143 144 144 144 147 150 152 156 157 157 160 161 163 163 164 164 165 168 Flash Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 19-4572; Rev 0; 4/09able of ContentsTable able of Table Table of Contents ZLF645 Series Flash MCUs Product Specification viii Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Option Bit Shadow Register Loading By Reset . . . . . . . . . . . . . . . . . . User Option Bit Locations in Flash Memory . . . . . . . . . . . . . . . . . . . . User Option Bit Shadow Register Access . . . . . . . . . . . . . . . . . . . . . . User Option Byte 0 and Option Byte 0 Shadow Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Option Byte 1 and Option Byte 1 Shadow Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 171 172 172 172 173 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 19-4572; Rev 0; 4/09able of ContentsTable able of Table Table of Contents ZLF645 Series Flash MCUs Product Specification 1 Architectural Overview Maxim's ZLF645 Series of Flash MCU's are members of the Crimzon(R) family of infrared microcontrollers. This series provides a directly-compatible code upgrade path to other Crimzon MCUs, offers a robust learning function, and features up to 64 KB Flash memory and 1K general-purpose Random Access Memory (RAM). Two timers allow the generation of complex signals while performing other counting operations. A Universal Asynchronous Receiver/Transmitter (UART) allows the ZLF645 MCU to function as a slave/master database chip. When the UART is not in use, the Baud Rate Generator (BRG) can be used as a third timer. Enhanced Stop Mode Recovery features allow the ZLF645 MCU to recover from STOP mode on any change of logic and on any combination of the 12 SMR inputs. The SMR source can also be used as an interrupt source. Many high-end remote control units offer a learning function. A learning function allows a replacement remote unit to learn infrared signals from the original remote unit and regenerate the signal. However, the amplifying circuits of many learning remotes are expensive and are not tuned well. The ZLF645 MCU is the first chip to offer a built-in tuned amplification circuit in a wide range of positions and battery voltages. The only external component required is a photodiode. The ZLF645 MCU greatly reduces the system cost and improves learning function reliability. With all new features, the ZLF645 MCU is excellent for infrared remote control and other MCU applications. Features Table 1 lists the memory, I/O, and power features of the ZLF645 Flash MCU. Additional features are listed below the table. Table 1. ZLF645 Flash MCU Features Device ZLF645 Flash MCU Flash (KB) 32 or 64 RAM* 512 B or 1 K I/O Lines 16, 24, or 40 Voltage Range 2.0 V-3.6 V *General-purpose registers implemented as RAM. PS026408-1208 Architectural Overview ZLF645 Series Flash MCUs Product Specification 2 Interrupt Sources The ZLF645 MCU supports 23 interrupt sources with 6 interrupt vectors, as given below: * * * * * Three external interrupts. Two from T8, T16 time-out and capture. Three from UART Tx, UART Rx, and UART BRG. One from LVD. Fourteen from SMR source P20-P27, P30-P33, P00, and P07: - Any change in logic from P20-P27, P30-P33 can generate an interrupt or SMR Additional Features The additional features of ZLF645 MCU include: * * * IR learning amplifier. Low power consumption--11 mW (typical). Three standby modes: - - - STOP--1.7 A (typical) HALT--0.6 mA (typical) Low-voltage reset * Intelligent counter/timer architecture to automate generation or reception and demodulation of complex waveform, and pulsed signals: - - - - One programmable 8-bit counter/timer with two capture registers and two load registers One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair Programmable input glitch filter for pulse reception The UART baud rate generator can be used as another 8-bit timer, when the UART is not in use Three external/UART interrupts Two assigned to counter/timers One low-voltage detection interrupt * Six priority interrupts: - - - PS026408-1208 Features ZLF645 Series Flash MCUs Product Specification 3 * 8-bit UART: - - - - RX and TX interrupts 4800, 9600, 19200, and 38400 baud rates Parity Odd/Even/None Stop bits 1/2 * * * * * * ICP (In-circuit Flash Programming) interface multiplexed with one of the GPIO's. Intelligent Power-On Reset (POR) to provide reduced POR time on detection of stable clock from external crystal oscillator or resonator. Low-voltage and high-voltage detection flags. Programmable Watchdog Timer (WDT)/POR circuits. Two on-board analog comparators with independent reference voltages and programmable interrupt polarity. User-selectable options through option bit Flash coding (ON/OFF): - Port 0 pins 0-3 pull-up transistors - Port 0 pins 4-7 pull-up transistors - Port 1 pins 0-3 pull-up transistors - Port 1 pins 4-7 pull-up transistors - Port 2 pins 0-7 pull-up transistors - Port 3 pins 0-3 pull-up transistors - Port 4 pins 0-7 pull-up transistors - WDT enabled at Power-On Reset - Flash lowest half main memory protect - Flash entire main memory protect - 16-bit addressability for stack pointer - No division, divide by 2, divide by 16, or divide by 32 of external clock to system clock Note: All signals with an overline, " ", are active Low. For example, B/W, in which WORD is active Low, and B/W, in which BYTE is active Low. Power connections use the conventional descriptions listed in Table 2. Table 2. Power Connections Connection Power Ground Device VDD VSS PS026408-1208 Features ZLF645 Series Flash MCUs Product Specification 4 Functional Block Diagram Figure 1 displays the functional blocks of the ZLF645 Flash MCU. Directional I/O Nibble Programmable P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 4 Register File 512 B/1 K x 8-Bit Port 0 Machine Timing & Register Bus Internal Address Bus Z8(R) LXMC Core Internal Data Bus Port 1 Expanded Register File Register Bus Two Comparators Instruction Control XTAL2 XTAL1 RESET 4 Flash Up to 64 KB x 8-Bit 8 Power-On Reset Directional I/O Byte Programmable Low-Voltage/ High-Voltage Detection 8-Bit Timer with UART Directional I/O Bit Programmable Port 2 8-Bit Timer Fix CMOS Input Port 3 16-Bit Timer Fix Push Pull Output IR Learning Amplification Directional I/O Bit Programmable Port 4 Figure 1. ZLF645 Flash MCU Functional Block Diagram PS026408-1208 Functional Block Diagram ZLF645 Series Flash MCUs Product Specification 5 Pin Description Figure 2 displays the pin configuration for ZLF645 MCU 20-pin QFN packages. 15 14 13 12 11 16 17 18 19 10 9 8 7 6 2 3 4 5 Figure 2. 20-Pin QFN Pin Configuration 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 6 Table 3 lists the function and signal directions of each pin within the 20-pin QFN package sequentially by pin number. Table 3. 20-Pin QFN Sequential Pin Identification Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 P36 P00 P30 P01 GND P20 P21 P22 P23 P24 P25 P26 P27 Function Port 0, bit 7 Power Supply Crystal oscillator Crystal oscillator Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 3, bit 6 Port 0, bit 0 Port 3, bit 0 Port 0, bit 1 Ground In Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4 Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Signal Direction Input/Output Input Output Input Input Input Input Input/Output Output Input/Output Input Input/Output put Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Note: When the Port 0 low-nibble pull-up option is enabled and the P30 input is Low, current flows through the pull-up to Ground. 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 7 Table 4 lists the function and signal direction of each pin within the 20-pin QFN package by function. Table 4. 20-Pin QFN Functional Pin Identification Pin No 10 11 1 13 14 15 16 17 18 19 20 5 6 7 8 9 2 12 4 3 Symbol P00 P30 P01 P07 P20 P21 P22 P23 P24 P25 P26 P27 P31 P32 P33 P34 P36 VDD GND XTAL1 XTAL2 Function Port 0, bit 0 Port 3, bit 0 Port 0, bit 1 Port 0, bit 7 Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4 Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 3, bit 6 Power Supply Ground In Crystal oscillator Crystal oscillator Signal Direction Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input/Output Output Input put Input Output Note: When the Port 0 low-nibble pull-up option is enabled and the P30 input is Low, current flows through the pull-up to Ground. 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 8 Figure 3 displays the pin configuration for ZLF645 MCU 20-pin PDIP, SOIC, and SSOP packages. P25 P26 P27 P07 VDD XTAL2 XTAL1 P31 P32 P33 1 2 3 4 5 6 7 8 9 10 20-Pin PDIP SOIC SSOP 20 19 18 17 16 15 14 13 12 11 P24 P23 P22 P21 P20 VSS P01 P00/P30 P36 P34 Figure 3. 20-Pin PDIP/SOIC/SSOP Pin Configuration 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 9 Table 5 lists the function and signal directions of each pin within the 20-pin PDIP, SOIC, and SSOP packages sequentially by pin number. Table 5. 20-Pin PDIP/SOIC/SSOP Sequential Pin Identification Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol P25 P26 P27 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 P36 P00 P30 P01 VSS P20 P21 P22 P23 P24 Function Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 0, bit 7 Power Supply Crystal oscillator Crystal oscillator Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 3, bit 6 Port 0, bit 0 Port 3, bit 0 Port 0, bit 1 Ground In Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4 Signal Direction Input/Output Input/Output Input/Output Input/Output Input Output Input Input Input Input Input/Output Output Input/Output Input Input/Output put Input/Output Input/Output Input/Output Input/Output Input/Output Note: When the Port 0 low-nibble pull-up option is enabled and the P30 input is Low, current flows through the pull-up to Ground. 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 10 Table 6 lists the function and signal direction of each pin within the 20-pin PDIP, SOIC, and SSOP packages by function. Table 6. 20-Pin PDIP/SOIC/SSOP Functional Pin Identification Pin No 13 14 4 16 17 18 19 20 1 2 3 8 9 10 11 12 5 15 7 6 Symbol P00 P30 P01 P07 P20 P21 P22 P23 P24 P25 P26 P27 P31 P32 P33 P34 P36 VDD VSS XTAL1 XTAL2 Function Port 0, bit 0 Port 3, bit 0 Port 0, bit 1 Port 0, bit 7 Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4 Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 3, bit 6 Power Supply Ground In Crystal oscillator Crystal oscillator Signal Direction Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input/Output Output Input put Input Output Note: When the Port 0 low-nibble pull-up option is enabled and the P30 input is Low, current flows through the pull-up to Ground. 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 11 Figure 4 displays the pin configuration of the ZLF645 MCU within the 28-pin PDIP, SOIC, and SSOP packages. P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-Pin PDIP SOIC SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35 Figure 4. 28-Pin PDIP/SOIC/SSOP Pin Configuration 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 12 Table 7 lists the function and signal directions of each pin within the 28-pin PDIP, SOIC, and SSOP packages sequentially by pin number. Table 7. 28-Pin PDIP/SOIC/SSOP Sequential Pin Identification Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 P35 P37 P36 P30 P00 P01 P02 VSS P03 P20 P21 P22 P23 P24 Function Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 0, bit 4 Port 0, bit 5 Port 0, bit 6 Port 0, bit 7 Power supply Crystal oscillator Crystal oscillator Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 3, bit 5 Port 3, bit 7 Port 3, bit 6 Port 3, bit 0; connect to VDD if not used Port 0, bit 0 Port 0, bit 1 Port 0, bit 2 Ground Port 0, bit 3 Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4 Signal Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Output Input Input Input Input Input/Output Output Output Output Input Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 13 Table 8 lists the functions and signal directions of each pin within the 28-pin PDIP, SOIC, and SSOP packages by function. Table 8. 28-Pin PDIP/SOIC/SSOP Functional Pin Identification Pin No 19 20 21 23 4 5 6 7 24 25 26 27 28 1 2 3 18 11 12 13 14 15 17 16 8 22 10 9 Symbol P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 VDD VSS XTAL1 XTAL2 Function Port 0, bit 0 Port 0, bit 1 Port 0, bit 2 Port 0, bit 3 Port 0, bit 4 Port 0, bit 5 Port 0, bit 6 Port 0, bit 7 Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4 Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 3, bit 0; connect to VDD if not used Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 3, bit 5 Port 3, bit 6 Port 3, bit 7 Power supply Ground Crystal oscillator Crystal oscillator Signal Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input/Output Output Output Output Input Input Input Output 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 14 Figure 5 displays the pin configuration of the ZLF645 MCU within the 48-pin SSOP package. P40 P25 P26 P27 P04 P41 P05 P06 P14 P15 P07 VDD VDD P42 P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 P43 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 48-Pin SSOP 37 36 35 34 33 32 31 30 29 28 27 26 25 P47 P46 P24 P23 P22 P21 P20 P03 P13 P12 VSS VSS P45 P02 P11 P10 P01 P00 P44 P30/PREF1 P36 P37 P35 /RESET Figure 5. 48-Pin SSOP Pin Configuration Table 9 lists the functions and signal directions of each pin within the 48-pin SSOP package sequentially by pin number. Table 9. 48-Pin SSOP Sequential Pin Identification Pin No 1 2 3 4 5 6 7 Symbol P40 P25 P26 P27 P04 P41 P05 Function Port 4, bit 0 Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 0, bit 4 Port 4, bit 1 Port 0, bit 5 Signal Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 15 Table 9. 48-Pin SSOP Sequential Pin Identification (Continued) Pin No 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol P06 P14 P15 P07 VDD VDD P42 P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 P43 VSS /RESET P35 P37 P36 P30/PREF1 P44 P00 P01 P10 P11 P02 P45 VSS VSS P12 P13 Function Port 0, bit 6 Port 1, bit 4 Port 1, bit 5 Port 0, bit 7 Power Supply Power Supply Port 4, bit 2 Port 1, bit 6 Port 1, bit 7 Crystal oscillator Crystal oscillator Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 4, bit 3 Ground Bidirectional reset signal Port 3, bit 5 Port 3, bit 7 Port 3, bit 6 Port 3, bit 0 Port 4, bit 4 Port 0, bit 0 Port 0, bit 1 Port 1, bit 0 Port 1, bit 1 Port 0, bit 2 Port 4, bit 5 Ground Ground Port 1, bit 2 Port 1, bit 3 Signal Direction Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Output Input Input Input Input Input/Output Input/Output Input Input/Output Output Output Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 16 Table 9. 48-Pin SSOP Sequential Pin Identification (Continued) Pin No 41 42 43 44 45 46 47 48 Symbol P03 P20 P21 P22 P23 P24 P46 P47 Function Port 0, bit 3 Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4 Port 4, bit 6 Port 4, bit 7 Signal Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Table 10 lists the functions and signal directions of each pin within the 48-pin SSOP package by function. Table 10. 48-Pin SSOP Functional Pin Identification Pin No 31 32 35 41 5 7 8 11 33 34 39 40 9 10 15 16 42 43 44 Symbol P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 Function Port 0, bit 0 Port 0, bit 1 Port 0, bit 2 Port 0, bit 3 Port 0, bit 4 Port 0, bit 5 Port 0, bit 6 Port 0, bit 7 Port 1, bit 0 Port 1, bit 1 Port 1, bit 2 Port 1, bit 3 Port 1, bit 4 Port 1, bit 5 Port 1, bit 6 Port 1, bit 7 Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Signal Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 17 Table 10. 48-Pin SSOP Functional Pin Identification (Continued) Pin No 45 46 2 3 4 29 19 20 21 22 26 28 27 1 6 14 23 30 36 47 48 12 13 24 37 38 18 17 25 Symbol P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 VDD VDD VSS VSS VSS XTAL1 XTAL2 /RESET Function Port 2, bit 3 Port 2, bit 4 Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 3, bit 0; connect to VDD if not used Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 3, bit 5 Port 3, bit 6 Port 3, bit 7 Port 4, bit 0 Port 4, bit 1 Port 4, bit 2 Port 4, bit 3 Port 4, bit 4 Port 4, bit 5 Port 4, bit 6 Port 4, bit 7 Power Supply Power Supply Ground Ground Ground Crystal oscillator Crystal oscillator Bidirectional reset signal Signal Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input/Output Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input Input Output Input/Output 19-4572; Rev 0; 4/09 Pin Description ZLF645 Series Flash MCUs Product Specification 18 I/O Port Pin Functions The ZLF645 MCU features up to five 8-bit ports which are described below: 1. Port 0 is nibble-programmable as either input or output. 2. Port 1 is byte-programmable as either input or output. 3. Port 2 is bit-programmable as either input or output. 4. Port 3 features four inputs on the lower nibble and four outputs on the upper nibble. 5. Port 4 is bit-programmable as either input or output. Note: Port 0, Port 1, Port 2, and Port 4 internal pull-ups are disabled on any pin or group of pins when programmed into output mode. Caution: The CMOS input buffer for each Port 0, Port 1, Port 2, or Port 4 pin are always connected to the pin, even when the pin is configured as an output. If the pin is configured as an open-drain output and no external signal is applied, a High output state can cause the CMOS input buffer to float. This may lead to excessive leakage current of more than 100 A. To prevent this leakage, connect the pin to an external signal with a defined logic level or ensure that its output state is Low, especially during STOP mode. Port 0, Port 1, Port 2, and Port 4 have both input and output capability. The input logic is always present no matter whether the port is configured as input or output. When executing a READ instruction, the MCU reads the actual value at the input logic but not from the output buffer. In addition, the instructions of OR, AND, and XOR have the ReadModify-Write sequence. The MCU first reads the port, then modifies the value, and loads back to the port. Precaution must be taken, if the port is configured as an open-drain output or if the port is driving any circuit that makes the voltage different from the appropriate output logic. If it is configured as open-drain output with output logic as ONE, it is a floating port and reads back as ZERO. The following instruction sets P00-P07 all Low: AND P0,#%F0 RESET (Input, Active Low) Reset initializes the MCU and is accomplished either through Power-On Reset (POR), Watchdog Timer (WDT), Stop Mode Recovery, Low-Voltage detection, or through the external reset pin in the case of 48-pin packaged products. PS026408-1208 I/O Port Pin Functions ZLF645 Series Flash MCUs Product Specification 19 During POR and WDT Reset, the internally generated reset drives the reset pin Low for the POR time. Any device driving the external reset line must be open-drain to avoid damage from a possible conflict during reset conditions. A pull-up is provided internally for the reset pin, if available. When the ZLF645 MCU asserts (Low) the RESET pin, the internal pull-up is disabled. The ZLF645 MCU does not assert the RESET pin when the VDD voltage is below the VBO trip point level (for more details, see Reset and Power Management on page 137). Note: The external reset does not initiate an exit from STOP mode. Table 11 lists the registers used to control I/O ports. Some port pin functions can also be affected by control registers for other peripheral functions. Table 11. I/O Port Control Registers Address (Hex) 12-Bit 000 001 002 003 F08 F09 0F6 0F7 0F8 F00 Bank 0-3 0-3 0-3 0-3 0-3 F All All All F 8-Bit 00 01 02 03 08 09 F6 F7 F8 00 Register Description Port 0 Register Port 1 Register Port 2 Register Port 3 Register Port 4 Register Port 4 Mode Register Port 2 Mode Register Port 3 Mode Register Port 0/1 Mode Register Port Configuration Register Mnemonic P0 P1 P2 P3 P4 P4M P2M P3M P01M PCON Reset XXh XXh XXh 0Xh XXh FFh FFh XXXX_X000b X 1 X X _ X XX1 b XXXX_1 110b Page No 32 33 35 37 40 39 34 36 31 30 PS026408-1208 RESET (Input, Active Low) ZLF645 Series Flash MCUs Product Specification 20 Port 0 Port 0 is an 8-bit bidirectional CMOS-compatible port. Its eight I/O lines are configured under software control to create a nibble I/O port. The output drivers are push/pull or open-drain, controlled by bit 2 of the Port Configuration Register. If one or both nibbles are required for I/O operation, they must be configured by writing to the Port 0/1 Mode Register. After a hardware reset or a Stop Mode Recovery, Port 0 is configured as an input port. Port 0, bit 7 is used as the transmit output of the UART when UART Tx is enabled. The I/O function of Port 0, bit 7 is overridden by the UART serial output (TxD) when UART Tx is enabled (UCTL[7] = 1). The pin must be configured as an output for TxD data to reach the pin (P01M[6] = 0). An optional pull-up transistor is available as an user-selectable flash programming option on all Port 0 bits with nibble select. Figure 6 displays the Port 0 configuration. 4 ZLF645 FLASH MCU Port 0 (I/O) 4 Open-Drain I/O VDD Resistive pull-up transistor Flash Programming Option Pad Out In Figure 6. Port 0 Configuration PS026408-1208 Port 0 ZLF645 Series Flash MCUs Product Specification 21 Port 1 Port 1 is an 8-bit bidirectional CMOS-compatible I/O port. It can be configured under software control as inputs or outputs. A flash programming option bit is available to connect eight pull-up transistors on this port. Bits programmed as output are globally programmed as either push/pull or open-drain. The power-on reset function resets with the eight bits of Port 1 [P17:10] configured as inputs. Figure 7 displays the Port 1 configuration. ZLF645 FLASH MCU 8 Port 1 (I/O) Open-Drain I/O VDD Resistive pull-up transistor Flash Programming Option Pad Out In Figure 7. Port 1 Configuration PS026408-1208 Port 1 ZLF645 Series Flash MCUs Product Specification 22 Port 2 Port 2 is an 8-bit bidirectional CMOS-compatible I/O port. Its eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A flash programming option bit is available to connect eight pull-up transistors on this port. Bits programmed as outputs are globally programmed as either push/pull or open-drain. The Power-On Reset function resets with the eight bits of Port 2 [P27:20] configured as inputs. Port 2 also has an 8-bit input OR and AND gate and edge detection circuitry, which can be used to recover from the STOP mode. P20 can be programmed to access the edge-detection circuitry in DEMODULATION mode. Figure 8 displays the Port 2 configuration. ZLF645 FLASH MCU Port 2 (I/O) Open-Drain I/O VDD Resistive pull-up transistor Flash Programming Option Pad Out In Figure 8. Port 2 Configuration PS026408-1208 Port 2 ZLF645 Series Flash MCUs Product Specification 23 Port 3 Port 3 is an 8-bit CMOS-compatible I/O port. Port 3 consists of four fixed inputs (P33:P30), three fixed outputs (P37:P36:P35), and one multi-functioned pin (P34) that can function as an output only or as a bidirectional open-drain I/O depending on whether the ZLF645 MCU is in ICP mode. P30, P31, P32, and P33 are standard CMOS inputs with option enabled pull-up transistors and can be configured under software as interrupts, as received data input to the UART block, as input to comparator circuits, or as input to the IR learning amplifier. P37, P36, and P35 are push/pull outputs and can be configured as outputs from counter/timers and/or comparator circuits. During the ZLF645's POR time, P34 is configured as an input pin with pull-up enabled. If after completing it's POR period, the ZLF645 has not detected this pin LOW and been put into ICP mode, this pin will revert back to being a push/pull output only. For more details on the function of pin P34, see ICP Interface on page 53. PS026408-1208 Port 3 ZLF645 Series Flash MCUs Product Specification 24 Figure 9 displays the Port 3 configuration. ZLF645 FLASH MCU Figure 9. Port 3 Configuration P31 can be used as an interrupt, analog comparator input, infrared learning amplifier input, normal digital input pin, and as a Stop Mode Recovery source. When bit 2 of the Port 3 Mode register (P3M) is set, P31 is used as the infrared learning amplifier, IR1. The reference source for IR1 is GND. The infrared learning amplifier is disabled during STOP mode. When bit 1 of P3M is set, the part is in ANALOG mode and the analog comparator, PS026408-1208 Port 3 ZLF645 Series Flash MCUs Product Specification 25 COMP1 is used. The reference voltage for COMP1 is P30 (PREF1). When in ANALOG mode, P30 cannot be read as a digital input when the CPU reads bit 0 of the Port 3 register; such reads always return a value of 1. Also, when in ANALOG mode, P31 cannot be used as a Stop Mode Recovery source, as in STOP mode the comparator is disabled and its output will not toggle. The programming of bit 2 of the P3M register takes precedence over the programming of Bit 1 in determining the function of P31. If both bits are set, P31 functions as an IR learning amplifier instead of an analog comparator. As displayed in Figure 9 the output of the function selected for P31 can be used as a source for IRQ2 interrupt assertion. The IRQ2 interrupt can be configured based upon detecting a rising, falling, or edge-triggered input change using Bits 6 and 7 of the IRQ register. The P31 output stage signal also goes to the Counter/Timer edge detection circuitry in the same way that P20 does. P32 can be used as an interrupt, analog comparator, UART receiver, normal digital input and as Stop Mode Recovery source. When bit 6 of UCTL register is set, P32 functions as a receive input for the UART. When bit 1 of the P3M register is set, thereby placing Port 3 into ANALOG mode, P32 functions as an analog comparator, COMP2. The reference voltage for COMP2 is P33 (PREF2). P32 can be used as a rising, falling or edge-triggered interrupt, IRQ0, using IRQ register bits 6 and 7. If UART receiver interrupts are not enabled, the UART receive interrupt is used as the source of interrupts for IRQ0 instead of P32. When in ANALOG mode P32 cannot be used as SMR source because the comparators are turned OFF in STOP mode. When in ANALOG mode, P33 cannot be read by the CPU as a digital input through bit 3 of the Port 3 register. In this case, a read of bit 3 of the Port 3 register indicates whether Stop Mode Recovery condition exists. Reading a value of 0 indicates an SMR condition; if the ZLF645 MCU is in STOP mode, it will exit STOP mode. Reading a value of 1 indicates that no condition exists to exit the ZLF645 MCU from STOP mode. Additionally, when in ANALOG mode, P33 cannot be used as an interrupt source. Instead, the existence of a SMR condition can generate an interrupt, if enabled. P33 can be used as a falling-edge interrupt, IRQ1, when not in ANALOG mode. IRQ1 is also used as the UART TX interrupt and the UART BRG interrupt. Only one source is active at a time. If bit 7 and bit 5 of UCTL are set to 1, IRQ1 will transmit an interrupt when the Transmit Shift register is empty. If bits 0 and 5 of UCTL are set to 1 and bit 6 of UCTL is cleared to 0, the BRG interrupts will activate IRQ1. Note: Comparators and the IR amplifier are powered down by entering STOP mode. For P30:P33 to be used as a Stop Mode Recovery source during STOP mode, these inputs must be placed into DIGITAL mode. When in ANALOG mode, do not configure any Port 3 input as a SMR source. The configuration of these inputs must be re-initialized after Stop Mode Recovery or POR. PS026408-1208 Port 3 ZLF645 Series Flash MCUs Product Specification 26 2 Table 12. Summary of Port 3 Pin Functions In-Circuit Programmer Counter/Timers IN Pin P30 P31 P32 P33 P34 P35 P36 P37 I/O IN IN IN IN IN/OUT OUT Comparator REF1 AN1 AN2 REF2 Interrupt IRQ2 IRQ0 IRQ1 IRAMP IR1 UART UART Rx IROUT ICP T8 T16 AO1 OUT T8/T16 OUT AO2 Port 3 also provides output for each of the counter/timers and AND/OR Logic (see Figure 10). Control is performed by programming CTR1 bit 5 and bit 4, CTR0 bit 0, and CTR2 bit 0. PS026408-1208 Port 3 ZLF645 Series Flash MCUs Product Specification 27 VDD Resistive Pull-Up Transistor CTR0, bit 0 ICP P34 Data T8_Out PCON, bit 0 MUX VDD MUX P3M D2 P31 I REF + - MUX Pad P34 IR1 P3M D1 CTR2, bit 0 + - *See also In-Circuit Programmer chapter on P34 usage VDD P30 Comp1 P35 Data T16_Out MUX Pad P35 CTR1, bit 6 VDD P36 Data T8/16_Out MUX Pad P36 PCON, bit 0 VDD P37 Data P3M D1 P32 P32 P33 + - MUX Pad P37 Comp2 Figure 10. Port 3 Counter/Timer Output Configuration PS026408-1208 Port 3 ZLF645 Series Flash MCUs Product Specification 28 Comparator Inputs In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference is supplied by P33 and PREF1. In ANALOG mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the Stop Mode Recovery sources (excluding P31, P32, and P33) as displayed in Figure 9 on page 24. In DIGITAL mode, P33 is used as bit 3 of the Port 3 input register, which then generates IRQ1. Note: Comparators are powered down by entering STOP mode. For P30:P33 to be used as an SMR source, these inputs must be placed into DIGITAL mode. Comparator Outputs The comparators can be programmed to output on P34 and P37 by setting bit 0 of the PCON register. Port 4 Port 4 is an 8-bit bidirectional CMOS-compatible I/O port. Its eight I/O lines can be independently configured under software control as inputs or outputs. Port 4 is always available for I/O operation. A flash programming option bit is available to connect eight pull-up transistors on this port. Bits programmed as outputs are globally programmed as either push/pull or open-drain. The POR function resets with the eight bits of Port 4 [P47:40] configured as inputs. Figure 11 on page 29 displays the Port 4 configuration. PS026408-1208 Port 4 ZLF645 Series Flash MCUs Product Specification 29 ZLF645 FLASH MCU Port 4 (I/O) Open-Drain I/O VDD Resistive pull-up transistor Flash Programming Option Pad Out In Figure 11. Port 4 Configuration PS026408-1208 Port 4 ZLF645 Series Flash MCUs Product Specification 30 Port Configuration Register The Port Configuration register (see Table 13) configures the Port 0 output mode and the comparator output on Port 3. The PCON register is located in expanded register Bank F, address 00h. Table 13. Port Configuration Register (PCON) Bit Field Reset R/W Address Bit Position [7:4] -- [3] 0 1 Value Description Reserved--Must be written to 1; reads 11111b. Port 4 Output Mode--Controls the output mode of Port 4. Open-drain Push/pull Port 0 Output Mode--Controls the output mode of Port 0. Write only; read returns 1. Open-drain Push/pull Port 1 Output Mode--Controls the output mode of Port 1. Write only; read returns 1 Open-drain Push/pull Comparator or IR Amplifier Output Port 3--Select digital outputs or comparator, and IR amplifier outputs on P34 and P37. X -- X -- X -- X -- 7 6 5 4 3 Port 4 Output Mode 1 W 2 Port 0 Output Mode 1 W 1 Port 1 Output Mode 1 W 0 Comp/IR Amp Output Port 3 0 W Reserved Bank F: 00h; Linear: F00h [2] 0 1 [1] 0 1 [0] 0 1 Write only; read returns 1. P34 and P37 outputs are digital. P34 is Comparator 1 or IR Amplifier output, P37 is Comparator 2 output. Note: PCON register is not reset after a Stop Mode Recovery. Also, for package types other than the 48-pin package, writes to bit 3 and bit 1 have no effect. PS026408-1208 Port Configuration Register ZLF645 Series Flash MCUs Product Specification 31 Port 0/1 Mode Register The Port 0/1 Mode register (see Table 14) determines the I/O direction of Port 0 and Port 1. The Port 0 direction is nibble-programmable. Bit 6 controls the upper nibble of Port 0, bits [7:4]. Bit 0 controls the lower nibble of Port 0, bits [3:0]. The Port 1 direction is byte programmable. Table 14. Port 0/1 Mode Register (P01M) Bit Field Reset R/W Address Bit Position [7] [6] Value 0 0 1 -- 0 1 0 1 Description Reserved--Must be written to 1. Reads 1b. P07:P04 Mode Output Input Reserved--Must be written to 1. Reads 1's. Port 1 Mode Output Input P00:P03 Mode Output Input 7 Reserved X -- 6 P07:P04 Mode 1 W 5 X -- 4 X -- 3 Port 1 Mode 1 W 2 X -- 1 X -- 0 P03:P00 Mode 1 W Reserved Reserved Bank Independent: F8h; Linear: 0F8h [5:4]* [3]* [0] * For package types other than the 48-pin package, writes to bit 3 have no effect. Note: Only P00, P01, and P07 are available for ZLF645 Flash MCU 20-pin configuration. PS026408-1208 Port 0/1 Mode Register ZLF645 Series Flash MCUs Product Specification 32 Port 0 Register The Port 0 register (see Table 15) allows read and write access to the Port 0 pins. Table 15. Port 0 Register (P0) Bit Field Reset R/W Address 7 P07 X R/W 6 P06 X R/W 5 P05 X R/W 4 P04 X R/W 3 P03 X R/W 2 P02 X R/W 1 P01 X R/W 0 P00 X R/W Bank 0-3: 00h; Linear: 000h Bit Position [7] R/W Read 0 1 Write 0 1 Description Port 0 Pin 7--Available for I/O if UART Tx is disabled. Pin configured as input or output in P01M register. Pin level is Low. Pin level is High. Pin configured as output in P01M register, UCTL[7]=0. Assert pin Low. Assert pin High if configured as push-pull; make pin high-impedance if it is open-drain. Port 0 Pins 6-0--Each bit provides access to the corresponding Port 0 pin. Pin configured as input or output in P01M register. Pin level is Low. Pin level is High. Pin configured as output in P01M register. Assert pin Low. Assert pin High if configured as push-pull; make pin high-impedance if it is open-drain. [6:0] Read 0 1 Write 0 1 Note: Only P00, P01, and P07 are available for ZLF645 Flash MCU 20-pin configuration. PS026408-1208 Port 0 Register ZLF645 Series Flash MCUs Product Specification 33 Port 1 Register The Port 1 register (see Table 16) allows read and write access to the Port 1 pins. Table 16. Port 1 Register (P1) Bit Field Reset R/W Address 7 P17 X R/W 6 P16 X R/W 5 P15 X R/W 4 P14 X R/W 3 P13 X R/W 2 P12 X R/W 1 P11 X R/W 0 P10 X R/W Bank 0-3: 01h; Linear: 001h Note: For package types other than the 48-pin package, this register is available as a general-purpose register. Bit Position [7:0] Value Read 0 1 Write 0 1 Description Port 1 Pins 7-0--Each bit provides access to the corresponding Port 1 pin. Pin configured as input or output in P01M register. Pin level is Low. Pin level is High. Pin configured as output in P01M register. Assert pin Low. Assert pin High, if configured as push-pull; make pin high-impedance if it is open-drain. Note: For packages other than 48-pin package, this register is available as general-purpose register. PS026408-1208 Port 1 Register ZLF645 Series Flash MCUs Product Specification 34 Port 2 Mode Register The Port 2 Mode register (see Table 17) determines the I/O direction of each bit on Port 2. Bit 0 of the Port 3 Mode register determines whether the output drive is push/pull or open-drain. Table 17. Port 2 Mode Register (P2M) Bit Field Reset R/W Address Bit Position [7] [6] [5] [4] [3] [2] [1] [0] Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Defines P27 as output. Defines P27 as input. Defines P26 as output. Defines P26 as input. Defines P25 as output. Defines P25 as input. Defines P24 as output. Defines P24 as input. Defines P23 as output. Defines P23 as input. Defines P22 as output. Defines P22 as input. Defines P21 as output. Defines P21 as input. Defines P20 as output. Defines P20 as input. 7 P27 I/O Definition 1 W 6 P26 I/O Definition 1 W 5 P25 I/O Definition 1 W 4 P24 I/O Definition 1 W 3 P23 I/O Definition 1 W 2 P22 I/O Definition 1 W 1 P21 I/O Definition 1 W 0 P20 I/O Definition 1 W Bank Independent: F6h; Linear: 0F6h Note: Port 2 Mode register is not reset after a Stop Mode Recovery. PS026408-1208 Port 2 Mode Register ZLF645 Series Flash MCUs Product Specification 35 Port 2 Register The Port 2 register (see Table 18) allows read and write access to the Port 2 pins. Table 18. Port 2 Register (P2) Bit Field Reset R/W Address 7 P27 X R/W 6 P26 X R/W 5 P25 X R/W 4 P24 X R/W 3 P23 X R/W 2 P22 X R/W 1 P21 X R/W 0 P20 X R/W Bank 0-3: 02h; Linear: 002h Bit Position [7:0] Value Read 0 1 Write 0 1 Description Port 2 Pins 7-0--Each bit provides access to the corresponding Port 2 pin. Pin configured as input or output in P2M register. Pin level is Low. Pin level is High. Pin configured as output in P2M register. Assert pin Low. Assert pin High if configured as push-pull; make pin high-impedance if it is open-drain. PS026408-1208 Port 2 Register ZLF645 Series Flash MCUs Product Specification 36 Port 3 Mode Register The Port 3 Mode register (see Table 19) is used to configure the functionality of Port 3 inputs and the output mode of Port 2. When bit 2 is set, the IR Learning Amplifier is used instead of the COMP1 comparator, regardless of the value of bit 1. Table 19. Port 3 Mode Register (P3M) Bit 7 6 5 Reserved Field Reset R/W Address Bit Position [7:3] [2] R/W -- W Value -- 0 1 X -- X -- X -- X -- X -- 0 W 4 3 2 IR Learning Amplifier 1 DIGITAL/ ANALOG Mode 0 W 0 Port 2 Open-Drain 0 W Bank Independent: F7h; Linear: 0F7h Description Reserved--Must be written to 1. Reads return 11111b. IR Learning Amplifier disabled. IR Learning Amplifier enabled with P31 configured as amplifier input. DIGITAL/ANALOG Mode P30, P31, P32, P33 are digital inputs. P30, P32, and P33 are comparator inputs. If P3M[2]=0, P31 also function as a comparator input. If P3M[2]=1, P31 is the IR amplifier input. Port 2 open-drain. Port 2 push/pull. [1] W 0 1 [0] W 0 1 Note: Port 3 Mode register is not reset after a Stop Mode Recovery. PS026408-1208 Port 3 Mode Register ZLF645 Series Flash MCUs Product Specification 37 Port 3 Register The Port 3 register (see Table 20) allows read access to port pins P33 through P30 and write access to the port pins P37 through P34. Table 20. Port 3 Register (P3) Bit Field Reset R/W Address Bit Position [7] Value Write 0 1 [6] Write 0 1 [5] Write 0 1 [4] Write Description Port 3, Pin 7 Output--Writes to this bit do not affect the pin state if write-only register bit PCON[0] is set to1, which configures P37 as the Comparator 1 or IR Amplifier output. P37 asserted Low if PCON[0]=0. P37 asserted High if PCON[0]=0. A read returns the last value written to this bit. Port 3, Pin 6 Output--Writes to this bit do not affect the pin state if register bits CTR1[7:6]=01, which configures P36 as the Timer 8 and Timer 16 combined logic output. P36 asserted Low. P36 asserted High. A read returns the last value written to this bit. Port 3, Pin 5 Output--Writes to this bit do not affect the pin state if register bit CTR2[0]=1, which configures P35 as the Timer 16 output. P35 asserted Low. P35 asserted High. A read returns the last value written to this bit. Port 3, Pin 4 Output--Writes to this bit do not affect the pin state if write only register bit PCON[0]=1 which configures P34 as a Comparator 2 output, register bit CTR0[0]=1 which configures P34 as Timer 8 output, or if the device is in ICP mode as described in the ICP Interface on page 53. P34 asserted Low. P34 asserted High. A read returns the last value written to this bit. 7 P37 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 X R/W 2 P32 X R/W 1 P31 X R/W 0 P30 X R/W Banks 0-3: 03h; Linear: 003h 0 1 PS026408-1208 Port 3 Register ZLF645 Series Flash MCUs Product Specification 38 Bit Position [3] Value Read 0 1 0 1 Description Port 3, Pin 3 Input--Writing this bit has no effect. If P3M[1]=0: P33 is Low. P33 is High. If P3M[1]=1 or SMR4[4]=1: SMR condition exists. SMR condition does not exist. Port 3, Pin 2 Input--Writing this bit has no effect. If P3M[1]=0: P32 input is Low. P32 input is High. If P3M[1]=1: Comparator 2 output is Low. Comparator 2 output is High. Port 3, Pin 1 Input--Writing this bit has no effect. If P3M[2:1]=00: P31 input is Low. P31 input is High. If P3M[2:1]=01: Comparator 1 output is Low. Comparator 1 output is High. If P3M[2:1]=10 or 11: IR amplifier output is Low. IR amplifier output is High. Port 3, Pin 0 Input--Writing this bit has no effect. If P3M[1]=0: P30 input is Low. P30 input is High. If P3M[1]=1: Reads as 1. [2] Read 0 1 0 1 [1] Read 0 1 0 1 0 1 [0] Read 0 1 1 Note: Port 3 register is not reset after a Stop Mode Recovery. PS026408-1208 Port 3 Register ZLF645 Series Flash MCUs Product Specification 39 Port 4 Mode Register The Port 4 Mode register (see Table 21) determines the I/O direction of each bit on Port 4. Bit 3 of the Port Configuration register (PCON) determines whether the output drive is push/pull or open-drain. Table 21. Port 4 Mode Register (P4M) Bit Field Reset R/W Address Bit Position [7] [6] [5] [4] [3] [2] [1] [0] Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Defines P47 as output. Defines P47 as input. Defines P46 as output. Defines P46 as input. Defines P45 as output. Defines P45 as input. Defines P44 as output. Defines P44 as input. Defines P43 as output. Defines P43 as input. Defines P42 as output. Defines P42 as input. Defines P41 as output. Defines P41 as input. Defines P40 as output. Defines P40 as input. 7 P47 I/O Definition 1 W 6 P46 I/O Definition 1 W 5 P45 I/O Definition 1 W 4 P44 I/O Definition 1 W 3 P43 I/O Definition 1 W 2 P42 I/O Definition 1 W 1 0 P41 I/O P40 I/O Definition Definition 1 W 1 W Bank F: 09h; Linear: F09h Note: Port 4 Mode register is not reset after a Stop Mode Recovery. PS026408-1208 Port 4 Mode Register ZLF645 Series Flash MCUs Product Specification 40 Port 4 Register The Port 4 register (see Table 22) allows read and write access to the Port 4 pins. Table 22. Port 4 Register (P4) Bit Field Reset R/W Address 7 P47 X R/W 6 P46 X R/W 5 P45 X R/W 4 P44 X R/W 3 P43 X R/W 2 P42 X R/W 1 P41 X R/W 0 P40 X R/W Banks 0-3: 04h; Linear: 004h Bit Position [7:0] Value Read 0 1 Write 0 1 Description Port 4 Pins 7-0--Each bit provides access to the corresponding Port 4 pin. Pin configured as input or output in P4M register. Pin level is Low. Pin level is High. Pin configured as output in P4M register. Assert pin Low. Assert pin High if configured as push-pull; make pin high-impedance if it is open-drain. PS026408-1208 Port 4 Register ZLF645 Series Flash MCUs Product Specification 41 Memory and Registers The Z8(R) LXMC CPU used in the ZLF645 Series of Flash MCUs incorporates special features to extend the available memory space while maintaining the benefits of a Z8(R) CPU core in battery-operated applications. Flash Program/Constant Memory The ZLF645 Series of Flash MCUs can address up to 64 KB of Flash memory for object code (program instructions and immediate data) and constant data (ROM tables and data constants). The first 12 bytes of the memory are reserved for the six available 16-bit interrupt request (IRQ) vectors. On reset, program execution begins at address 000Ch in the memory. Execution rolls over to the beginning of the memory if the program counter address exceeds the Flash memory size. The entire Flash memory is available for either program code or constant data. Outside of normal instruction fetches, the CPU can access the Flash memory by using LDC and LDCI instructions. The LDC and LDCI instructions use 16-bit addresses to access the memory. Figure 12 displays the Program/Constant memory map for the device. FLASH Memory Up to 64 KB Program or Constants 000Ch (Reset) IRQ 0-5 Vectors 0000h = 16-bit Address (Not to Scale) Figure 12. Program/Constant Memory Map PS026408-1208 Memory and Registers ZLF645 Series Flash MCUs Product Specification 42 Register File The ZLF645 Series of Flash MCUs features up to 1024 bytes of register file space, organized in 256-byte banks. Bank 0 contains 235 or 237 bytes of RAM addressed as general purpose registers, 5 or 3 port addresses, and 16 control register addresses. For 20- or 28-pin packages, Port 1 and Port 4 registers of Bank 0 are not implemented and there locations are available as general-purpose registers. Bank 1, Bank 2, and Bank 3; each contain 256 general-purpose register bytes. Bank D and Bank F; each contain 16 addresses for control registers. All other banks are reserved and must not be selected. The current bank is selected for 8-bit direct or indirect addressing by writing Register Pointer bits RP[3:0]. In the current bank, a 16-byte working register group (addressed as R0-R15) is selected by writing RP[7:4]. A working register operand requires only 4 bits of Program Memory. There are 16 working register groups per bank (see Figure 13 and Figure 14). The 8-bit addresses in the range F0h-FFh (and the equivalent 4-bit addresses) are bank-independent, meaning they always access the control registers in Bank 0, regardless of the RP[3:0] value. Addresses in the range 00h-03h always access the Bank 0 Port registers unless Bank D or Bank F is selected (Port 01h is not implemented in this device). When Bank D or Bank F is selected, addresses 10h-EFh access the Bank 0 general- purpose registers. The LDX and LDXI instructions or indirect addressing is used to access the Bank 1-3 registers not accessible by 8-bit or working register addresses (12-bit addresses--100h- 103h, 1F0h-1FFh, 200h-203h, 2F0h-2FFh, 300h-303h, and 3F0h-3FFh). See Linear Memory Addressing on page 45. Stack The Stack Pointer register provides either 16-bit or 8-bit of stack pointer addressability depending upon the programming of bit 3 of User Option Byte 1 (for more details, see Flash Option Bits on page 171). 16-bit Stack Addressability When programmed for 16-bit stack addressability, the stack address is formed as a combination of the SPL and SPH registers located at addresses FFh and FEh. For 1K and 512 B RAM products, the most significant 6 or 5 bits, respectively of the SPH register are ignored. The stack address is mapped to a particular RAM memory location by the following formula: Bank = {2'b0, SPH[1:0]} Group = SPL[7:4] Register number = SPL[3:0] With the ZLF645 MCU configured for 16-bit stack addressability, stack reads or writes to Bank 3, 2, 1, or 0 Group F Registers or to any of the Port registers actually accesses PS026408-1208 Register File ZLF645 Series Flash MCUs Product Specification 43 shadow registers implemented within the RAM memory. This enables the entire 1K or 512 B, depending on the product, of the RAM memory to be used for the stack. 8-bit Stack Addressability For 8-bit stack addressability, only the SPL register is used for stack addressing and stack operations that use the stack pointer always address Bank 0, independent of the RP[3:0] setting. For more details on the stack, refer to Z8 (R) LXMC CPU Core User Manual (UM0215). When in 8-bit stack addressability mode, the Bank 0 register FEh can be used to store user data. See Stack Pointer Register on page 48. B anks 1-3 C P U C ontrol F 0 h-F F h C P U C ontrol F 0 h-F F h B ank 0 C P U C ontrol F 0 h-F F h B ank D C P U C ontrol F 0 h-F F h B ank F C P U C ontrol F 0 h-F F h C P U C ontrol F 0 h-F F h G eneral P urpose R egisters 05h-E F h G eneral P urpose R egisters 05h-E F h B ank D G eneral P urpose R egisters 10h-E F h B ank F G eneral P urpose R egisters 10h-E F h P orts 00h-04h ** P orts 00h-04h ** P eripheral C ontrol 0 0 h-0 F h P eripheral C ontrol 0 0 h-0 F h = Bank-Independent A ddress (A lw ays Accesses B ank 0 ) ** For 20 and 28 pin parts, the Port01 and P ort04 locations becom e available for use as general purpose registers Figure 13. Register File 8-Bit Banked Address Map PS026408-1208 Register File ZLF645 Series Flash MCUs Product Specification 44 Active Group Active Bank R7 R6 R5 R4 R3 R2 R1 R0 Register Pointer (RP), 0FDh The upper nibble of the register file address Provided by the register pointer specifies The active working group register FF F0 EF E0 DF D0 * * * 4F 40 3F 30 2F 20 1F 10 0F Specified Working Register Group Register Group 2 Register Group 1 Register Group 0 I/O Ports (Banks 0-3 Only) R15 to R0 R15 to R5 R4 to R0* The lower nibble of the register file address provided by the instruction points to the specified register Register Group F 00 * RP=00: selects Register Bank 0, Working Register Group 0 Figure 14. Register Pointer--Detail PS026408-1208 Register File ZLF645 Series Flash MCUs Product Specification 45 Register Pointer Example R253 R0 = R1 = R2 = R3 = R4 = RP = Port Port Port Port Port 00h 0 1 2 3 4 But if: R253 R0 = R1 = R2 = R3 = R4 = RP = 0Dh CTR0 CTR1 CTR2 CTR3 TC8L The counter/timers are mapped into ERF Group D. Access is easily performed using the following code segment: LD RP, #0Dh LD R0,#xx LD 1, #xx LD R1, 2 LD RP, #7Dh LD 71h, 2 LD R1, 2 ; ; ; ; ; ; ; ; ; Select ERF D for access to Bank D (working register group 0) load CTR0 load CTR1 CTR2 CTR1 Select Expanded Register Bank D and working register group 7 of Bank 0 for access. CTR2 register 71h CTR2 register 71h Linear Memory Addressing In addition to using the RP register to designate a bank and working register group for 8-bit or 4-bit addressing, programs can use 12-bit linear addressing to load a register in any other bank to or from a register in the current bank. Linear addressing is implemented through the LDX and LDXI instructions only. Linear addressing treats the register file as if all the registers are logically ordered end-to-end, as opposed to being grouped into banks and working register groups, as displayed in Figure 15 on page 47. For linear addressing, register file addresses are numbered sequentially from Bank 0, register 00h to Bank 0, register FFh, then continuing with Bank 1, register 00h, and so on up to Bank F, register FFh. Using the LDX and/or the LDXI instructions, either the target or destination register location can be addressed through a 12-bit linear address value stored in a general-purpose register pair. PS026408-1208 Register File ZLF645 Series Flash MCUs Product Specification 46 Example For example, the following code uses linear addressing for the source of a register transfer operation and uses a working register address for the target: SRP #%23 LD R0, #%55 SRP #%12 LD R6, #%03 LD R7, #%20 LD R0, @RR6 ;Set working register group 2 in bank 3 ;Load 55 into working register R0 in the current ;group and bank (linear address 320h) ;Set working register group 1 in bank 2 ;Load high byte of source linear address (0320h) ;Load low byte of source linear address (0320h) ;Load linear address 320h contents (55h) into ;working register R0 in the current group and ;bank (linear address 210h) In the above code, the source register is referred through a linear address value contained within registers R6 and R7, whereas the destination is referenced via the SRP setting and a working register. For more information about instructions on the usage of LDX and LDXI instructions, refer to Z8(R) LXMC CPU Core User Manual (UM0215). Note: The LDE and LDEI instructions that existed in the Z8 CPU are no longer valid; they have been replaced by the LDX and LDXI instructions. PS026408-1208 Register File ZLF645 Series Flash MCUs Product Specification 47 Banks 1-3 Bank 0 CPU Control F0h-FFh Bank D Bank F General Purpose Registers 100h-3FFh Reserved D10h-DFFh Reserved F10h-FFFh General Purpose Registers 05h-EFh Ports 00h-04h ** ** Peripheral Control D00h-D0Fh Peripheral Control F00h-F0Fh ** For 20 and 28 pin parts, the Port01 and Port04 locations become available for use as general purpose registers Figure 15. Register File LDX, LDXI Linear 12-Bit Address Map PS026408-1208 Register File ZLF645 Series Flash MCUs Product Specification 48 Register Pointer Register The upper nibble of the Register Pointer register (see Table 23) selects which working register group is accessed. A working register group consists of 16 bytes. The lower nibble selects the expanded register file bank; for ZLF645 MCU, Banks 0, 1, 2, 3, F, and D are implemented. A 0h in the lower nibble allows the normal register file (Bank 0) to be addressed. Any other value from 01h to 0Fh exchanges the lower 16 registers to an expanded register bank. Table 23. Register Pointer Register (RP) Bit Field Reset R/W Address Bit Position Value Description Working Register Group Pointer Determines which 16-byte working group is addressed. Register Bank Pointer Determines which bank is active. 7 6 5 4 3 2 1 0 Working Register Group Pointer 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Register Bank Pointer 0 R/W 0 R/W 0 R/W Bank Independent: FDh; Linear: 0FDh [7:4] [3:0] 0h-Fh 0h-Fh Stack Pointer Register Through a Flash programmable option bit, the Stack Pointer register of the ZLF645 MCU is either one or two bytes providing either 8-bit or 16-bit of stack addressing. When not enabled through the option bit for 16-bit stack addressability, the SPH register can be used as a User Data register (USER). The stack pointer resides in the RAM and when the ZLF645 MCU is programmed for 8-bit addressing, this stack pointer resides in Bank 0 of the RAM only. With 16-bit addressing, the entire RAM's address space is available for use as the stack. The stack address is decremented prior to a PUSH operation and incremented after a POP operation. The stack address always points to the data stored at the `top' of the stack (the lowest stack address). During a call instruction, the contents of the Program Counter are saved on the stack. Interrupts cause the contents of the Program Counter and Flags registers to be saved on the stack. An overflow or underflow can occur when the stack address is incremented or decremented during normal operations. You must prevent this occurrence or unpredictable operations may result (see Table 24 on page 49). PS026408-1208 Register Pointer Register ZLF645 Series Flash MCUs Product Specification 49 Table 24. Stack Pointer Register Low Byte (SPL) Bit Field Reset R/W Address Bit Position Value Description 7 6 5 4 3 2 1 0 Stack Pointer X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W Bank Independent: FFh; Linear: 0FFh [7:0] 00-FF Stack Pointer Table 25. Stack Pointer Register High Byte (SPH) or User Data Register (USER) Bit Field Reset R/W Address 7 6 5 4 3 2 1 0 Stack Pointer X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W Bank Independent: FEh; Linear: 0FEh Notes: 1. For devices with 1K bytes of RAM and with 16-bit stack pointer mode enabled, the upper 6 bits of this register are unused for stack addressing. For devices with 512 bytes of RAM and with 16-bit stack pointer mode enabled, the upper 7 bits of this register are unused for stack addressing. 2. When ZLF645 MCU is not in 16-bit stack pointer mode, this register is available to store use user data and its functionality is identical to other Maxim(R) Crimzon products such as the ZLP12840 and ZLR64400 MCUs. When available for user data, this register must not be used as a counter for the DJNZ instruction. PS026408-1208 Stack Pointer Register ZLF645 Series Flash MCUs Product Specification 50 Register File Summary Table 26 lists each linear (12-bit) register file address to the associated register, mnemonic, and reset value. The table also lists the register bank (or banks) and corresponding 8-bit address (if any) for each register and a page link to the detailed register table. Throughout this document, an `X' denotes an undefined digit. A `--' (dash) in a table cell indicates that the corresponding attribute does not apply to the listed item. Reset value digits (highlighted in grey) are not reset by a Stop Mode Recovery. Register bit SMR[7] (shown in boldface) is set to 1 instead of reset by a Stop Mode recovery. Table 26. Register File Address Summary Address (Hex) 12-Bit Bank 8-Bit Register Description Mnemonic Reset XXh XXh XXh 0Xh XXh XXh XXh Page No 000 001 002 003 004 0-3 0-3 0-3 0-3 0-3 00 01 02 03 04 Port 0 Register Port 1 Register Port 2 Register Port 3 Register Port 4 Register P0 P1 P2 P3 P4 -- -- -- 32 33 35 37 37 -- -- -- 95 95 97 98 -- 34 36 31 005-00F 0 05-0F General-Purpose Registers (Bank 0 Only) 010-0EF 0,D,F 10-EF General-Purpose Registers (Banks 0, D, F) 0F0 0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 All All All All All All All All All F0 F1 F2 F3 F4 F5 F6 F7 F8 Reserved -- XXh 0 0 0 0 _0 0 1 0 b 00h FFh -- FFh XXXX_X0 0 0 b X1 XX_1 XX1 b UART Receive/Transmit Data Register URDATA/ UTDATA UART Status Register UART Control Register UART Baud Rate Generator Constant Register Reserved Port 2 Mode Register Port 3 Mode Register Port 0/1 Mode Register UST UCTL BCNST -- P2M P3M P01M 19-4572; Rev 0; 4/09 Register File Summary ZLF645 Series Flash MCUs Product Specification 51 Table 26. Register File Address Summary (Continued) Address (Hex) 12-Bit Bank 8-Bit Register Description Mnemonic Reset XXh 00h 0 XXX_XXXXb XXh 00h XXh XXh XXh XXh XXh XXh XXh XXh XXh -- 0 0 0 0 _0 0 0 0 b 0 0 0 0 _0 0 0 0 b 0 0 0 0 _0 0 0 0 b 0 0 0 0 _0 XXXb 00h 00h 00h 00h 00h Page No 0F9 0FA 0FB 0FC 0FD 0FE 0FF 100-103 All All All All All All All -- F9 FA FB FC FD FE FF -- Interrupt Priority Register Interrupt Request Register Interrupt Mask Register Flags Register Register Pointer Register User Data Register/Stack Pointer Register High Byte1 Stack Pointer Register Low Byte General-Purpose Registers (12-Bit Only) General-Purpose Registers (12-Bit Only) General-Purpose Registers (12-Bit Only) General-Purpose Registers (12-Bit Only) Reserved Counter/Timer 8 Control Register Timer 8 and Timer 16 Common Functions Register Counter/Timer 16 Control Register Timer 8/Timer 16 Control Register Counter/Timer 8 Low Hold Register Counter/Timer 8 High Hold Register Counter/Timer 16 Low Hold Register Counter/Timer 16 High Hold Register Timer 16 Capture Low Register IPR IRQ IMR FLAGS RP USER/SPH SPL -- -- -- -- -- -- -- -- CTR0 CTR1 CTR2 CTR3 TC8L TC8H TC16L TC16H LO16 130 131 133 160 48 49 49 -- -- -- -- -- -- -- -- 119 121 124 126 118 117 117 116 116 104-1EF 1 1F0-203 -- 204-2EF 2 2F0-303 -- 304-3EF 3 3F0-3FF -- 400-CFF -- D00 D01 D02 D03 D04 D05 D06 D07 D08 D D D D D D D D D 04-EF General-Purpose Registers -- 04-EF General-Purpose Registers -- 04-EF General-Purpose Registers -- -- 00 01 02 03 04 05 06 07 08 19-4572; Rev 0; 4/09 Register File Summary ZLF645 Series Flash MCUs Product Specification 52 Table 26. Register File Address Summary (Continued) Address (Hex) 12-Bit Bank 8-Bit Register Description Mnemonic Reset 00h 00h 00h 1 1 1 1 _1 0 0 0 b -- FFH FFH -- XXXX_1 1 1 0 b Page No D09 D0A D0B D0C D0D D0E D0F F00 F01 F02 F03 F04 F09 F0A F0B F0C F0D F0E F0F 1When D D D D -- D D F F F F F F F F F F F F 09 0A 0B 0C 0E 0F -- 00 01 02 03 04 -- 09 0A 0B 0C 0D 0E 0F -- Timer 16 Capture High Register Timer 8 Capture Low Register Timer 8 Capture High Register Low-Voltage Detection Register ed User Option Byte 0 User Option Byte 1 Port Configuration Register Flash Page Select and Sector Protect Register Flash Frequency High Byte Register Flash Frequency Low Byte Register Reserved Port 4 Mode Register Stop Mode Recovery Register 4 Stop Mode Recovery Register Stop Mode Recovery Register 1 Stop Mode Recovery Register 2 Stop Mode Recovery Register 3 Watchdog Timer Mode Register HI16 LO8 HI8 LVD -- OPT0 OPT1 PCON FPS/FSEC FFREQH FFREQL -- P4M SMR4 SMR SMR1 SMR2 SMR3 WDTMR 115 115 114 140 -- 172 174 -- 30 -- Reserv D10-DFF -- Reserved (8-Bit access goes to Bank 0) -- Flash Control and Flash Status Register FCTL/FSTAT 0 0 0 0_0 0 0 0b 76/77 0 0 0 0_0 0 0 0b 78/79 0 0 0 0_0 0 0 0b 0 0 0 0_0 0 0 0b -- FFh XXX0 _0 0 0 0 b 0 0 1 0 _0 0 0 0 b 00h X0 X0 _0 0 XXb X0h 0 0 0 0 _1 1 0 1 b -- 80 80 -- 39 156 146 150 152 155 142 -- F05-F08 -- F10-FFF -- Reserved (8-Bit access goes to Bank 0) -- ZLF645 is programmed for 16-bit stack addressability, the value in this register is used as the high byte of a 16-bit stack pointer. 19-4572; Rev 0; 4/09 Register File Summary ZLF645 Series Flash MCUs Product Specification 53 ICP Interface The ICP interface of the ZLF645 is a single pin RS-232 like interface for performing programming, reads, and memory erasures to the ZLF645's Flash memory. For enabling the ZLF645 into ICP mode and for performing ICP operations, the ZLF645's P34 pin which normally functions as an output only is used. Enabling ICP Mode As mentioned previously, the ZLF645's GPIO pin P34 is multi-functioned to be used for putting the ZLF645 into ICP mode and for ICP communications once it is in that mode. Entry into ICP mode takes place during the ZLF645's power on reset period. During the ZLF645's power on reset period, the P34 pin which normally is an output only pin is configured by the ZLF645 as an input with pull-up enabled. If during this time this pin is driven LOW and held LOW until the end of the power on reset period, the ZLF645 will be put into ICP mode. Once in ICP mode, the P34 pin operates as an open-drain output bidirectional pin with pull-up enabled. The power on reset period as can be seen from the electrical specs section of this document can have a duration range of between 2.5 ms and 10 ms. To ensure proper entry into ICP mode, the P34 pin should be driven LOW and held low a minimum of 10 ms after power up. If during the ZLF645's power on reset period, the P34 pin is never driven LOW, pin p34 will be pulled HIGH through its pull-up device. In this case, if P34 remains HIGH until the end of the power on reset period, the ZLF645 will go into normal user mode and P34 will revert back to being an output pin only. To ensure proper entry into user mode when it is not intended to put the ZLF645 into ICP mode, it is important that in the customer application P34 only be connected to capacitive loads. This is due to the weak nature of its pull-up device, which can have a resistance ranging between 100 k up to 600 k depending on voltage, temperature, and process. State of ZLF645 in ICP Mode The operating characteristics of the device in ICP mode are: * * * * The CPU stops executing instructions. All on-chip peripherals are disabled. The ZLF645 constantly refreshes the Watchdog Timer, if enabled. The P34 pin is configured as a bidirectional pin with pull-up enabled and with the output stage configured as open-drain. The bidirectional control of the pins comes from the ICP Tx/Rx logic. 19-4572; Rev 0; 4/09 ICP Interface ZLF645 Series Flash MCUs Product Specification 54 Enabling Flash Accesses Through the ICP After the ZLF645 is in ICP mode, the FLASHCTL bit of the ICP Control register must be programmed to 1 before Flash accesses are enabled through the ICP interface. ICP Interface Logic Architecture The ICP logic within the ZLF645 MCU consists of four primary functional blocks: transmitter, receiver, auto-baud detector/generator, and Flash Controller interface. Figure 16 displays the architecture of the ICP. System Clock Auto-Baud Detector/Generator Z8 Flash Control Transmitter Flash Controller Interface ICP Pin Receiver Figure 16. In-Circuit Programmer Block Diagram ICP Interface Operation After the ZLF645 MCU is in ICP mode, pin P34 acts a bidirectional open-drain interface with internal pull-ups used for transmitting and receiving the data. Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously. Serial data on P34 is sent using the standard asynchronous data format defined in RS-232. This pin creates an interface from the ZLF645 MCU to the serial port of a host PC using minimal external hardware. Figure 17 displays the recommended method of connecting P34 pin to an RS-232 connection using an open-drain buffer. The ICP pin must always be connected to VDD through an external pull-up resistor. 19-4572; Rev 0; 4/09 Enabling Flash Accesses Through the ICP ZLF645 Series Flash MCUs Product Specification 55 Caution: For operation of the ICP, all power pins (VDD and AVDD) must be supplied with power and all ground pins (VSS and AVSS) must be properly grounded. VDD RS-232 Transceiver RS-232 TX 10 K ICP Pin Open-Drain Buffer RS-232 RX Figure 17. Interfacing the In-Circuit Programming Pin P34 with an RS-232 Interface (2) ICP Data Format The ICP interface uses the asynchronous data format defined for RS-232. Each character is transmitted as 1 Start bit, 8 data bits (least significant bit first), and 1.5 Stop bits (see Figure 18). START D0 D1 D2 D3 D4 D5 D6 D7 STOP Figure 18. ICP Data Format ICP Auto-Baud Detector/Generator To run over a range of baud rates (data bits per second) with various system clock frequencies, the ICP contains an Auto-Baud Detector/Generator. After a reset, the ICP is non-active until it receives data. The ICP requires that the first character sent from the host is character 80H. The character 80H has eight continuous bits Low (one Start bit plus 7 data bits), framed between High bits. The Auto-Baud Detector measures this period and sets the ICP Baud Rate Generator accordingly. The Auto-Baud Detector/Generator is clocked by the system clock. The minimum baud rate is the system clock frequency divided by 512. If the datastream can be synchronized with the system clock, the auto-baud generator can run as high as the system clock frequency divided by 2. 19-4572; Rev 0; 4/09 ICP Interface Operation ZLF645 Series Flash MCUs Product Specification 56 For optimal operation with asynchronous datastreams, the maximum recommended baud rate is the system clock frequency divided by 8. The maximum possible baud rate for asynchronous datastreams is the system clock frequency divided by 4, but this theoretical maximum is possible only for low noise designs with clean signals. Table 27 lists minimum and recommended maximum baud rates for sample crystal frequencies. Table 27. ICP Baud-Rate Limits System Clock Frequency (MHz) Recommended Maximum Baud Rate (Kbps) Recommended Standard PC Baud Rate (bps) Minimum Baud Rate (Kbps) 8.0 1.0 0.032768 (32 kHz) 1000.0 125.0 4.096 737280 115,200 2400 15.6 1.95 0.064 If the ICP receives a Serial Break (nine or more continuous bits Low) the Auto-Baud Detector/Generator resets. You can reconfigure the Auto-Baud Detector/Generator by sending character 80H. ICP Serial Errors The ICP can detect any of the following error conditions on the P34 pin when in ICP mode: * * * Serial Break (a minimum of nine continuous bits Low). Framing Error (received Stop bit is Low). Transmit Collision (ICP and host simultaneous transmission detected by the ICP). When the ICP detects one of these errors, it aborts any command currently in progress, transmits a four character long Serial Break back to the host, and resets the Auto-Baud Detector/Generator. A Framing Error or Transmit Collision can be caused by the host sending a Serial Break to the ICP. Because of the open-drain nature of the interface, returning a Serial Break break back to the host only extends the length of the Serial Break, if the host releases the Serial Break early. The host transmits a Serial Break on the ICP pin when first connecting to the device or recovering from an error. A Serial Break from the host resets the Auto-Baud Generator/ Detector but does not resets the ICP Control Register. A Serial Break leaves the device in DEBUG mode if that is the current mode. The ICP is held in Reset until the end of the Serial Break when the ICP pin returns High. Because of the open-drain nature of the ICP pin, the host can send a Serial Break to the ICP even if the ICP is transmitting a character. 19-4572; Rev 0; 4/09 ICP Interface Operation ZLF645 Series Flash MCUs Product Specification 57 As the ICP interface uses a single pin for both receive and transmit, it can only receive or transmit at a given time. For the most part, this is not a problem, as the ICP uses a host driven protocol (Z8(R) does not send any data without the host asking for it). To aid the ICP in avoiding collisions, the transmitter waits an additional 1/2 bit times after a Stop bit is fully received or transmitted before it starts transmission of a character. On the other hand, the receiver starts searching for a Start bit as soon as the middle of the Stop bit has been sampled and is valid. The transmitter does not start if another character is being received. ICP In-Circuit Programming Commands The host communicates to the ICP by sending ICP commands using the ICP interface. During normal operation, only a subset of the ICP commands are available. In FLASH CONTROL mode, all ICP commands are available, but for few commands their access to the Flash is qualified based upon the programming of the Flash Read/Write Protect Option bit (FLRWP) or the Lower Half Flash Read/Write Protect Option bit (FLPROT1). When either of these bits is enabled, some of the ICP commands will have reduced Flash memory access or will be disabled completely. Table 28 is a summary of the ICP commands. Each ICP command is described in further detail in the bulleted list following this table. Table 28 also indicates those commands that operate when the device is not in FLASH CONTROL mode (normal operation) and how those commands are effected by programming of the FLRWP and FLPROT1 Option bits. Table 28. In-Circuit Programmer Commands Disabled by Enabled when NOT Flash Read/Write Protect in FLASH CONTROL Option Bits (FLRWP and/or mode? FLPROT1) ICP Command Command Byte Read ICP Revision Reserved Read ICP Status Register Reserved Write ICP Control Register Read ICP Control Register Reserved Write Flash Controller Registers 00H 01H 02H 03H 04H 05H 06H - 07H 08H Yes -- Yes No Yes Yes No No -- -- -- -- -- -- 19-4572; Rev 0; 4/09 ICP In-Circuit Programming Commands ZLF645 Series Flash MCUs Product Specification 58 Table 28. In-Circuit Programmer Commands (Continued) Disabled by Enabled when NOT Flash Read/Write Protect in FLASH CONTROL Option Bits (FLRWP and/or mode? FLPROT1) ICP Command Command Byte Read Flash Controller Registers Write Flash Memory 09H 0AH No No -- If FLRWP en abled, comm and is disabled for en tire Flash main memory an d p age 3 of the Information Ar ea. If FLPROT1 enabled, co mmand disab led for page 3 of the In formation Are a and lower ha lf of ma in me mory only. If FLRWP en abled, comm and is disabled fo r t he F lash m ain memory. If FLPROT1 ena bled, command disabled for the lower half of main memory only. Disabled -- -- -- -- -- -- -- Read Flash Memory 0BH No Reserved Read Program Memory CRC Reserved Read ICP Autobaud Register Reserved Write Test Mode Register Read Test Mode Register Reserved 0CH - 0DH 0EH 0FH -1AH 1BH 1CH - EFH F0H F1H F2H - FFH -- No -- Yes -- Yes Yes -- In the following bulleted list of ICP commands, data and commands sent from the host to the ICP are identified by `ICP Command/Data'. Data sent from the ICP back to the host is identified by `ICP Data': * Read ICP Revision (00H)--The Read ICP Revision command determines the version of the ICP. If ICP commands are added, removed, or changed, the revision number changes. ICP 00H ICP ICPRev[15:8] (Major revision number) ICP ICPRev[7:0] (Minor revision number) 19-4572; Rev 0; 4/09 ICP In-Circuit Programming Commands ZLF645 Series Flash MCUs Product Specification 59 This command when executed returns a value of 0132H which is the revision ID assigned for the ZLF645 MCU. * Read ICP Status Register (02H)--The Read ICP Status register command reads the ICPSTAT register. ICP 02H ICP ICPSTAT[7:0] * Write ICP Control Register (04H)--The Write ICP Control register command writes the data that follows the command to the ICPCTL register. ICP 04H ICP ICPCTL[7:0] * Read ICP Control Register (05H)--The Read ICP Control register command reads the value of the ICPCTL register. ICP 05H ICP ICPCTL[7:0] * Write Flash Controller Registers (08H)--The Write Flash Controller register command allows writes to the Flash Controller registers. This command configures the Flash Controller for Flash memory accesses through the Write Flash Memory and Read Flash Memory commands. If the device is not in FLASH CONTROL mode, the register address and data values are discarded. ICP ICP ICP ICP ICP 08H Register Address[15:0] ("0FH" for all Flash Ctrl Regs) Register Address[7:0] Size[7:0] 1-256 data bytes * Read Flash Controller Registers (09H)--The Read Flash Controller command allows reads of the Flash Controller registers. If the device is not in FLASH CONTROL mode this command returns FFH for all the register values. ICP ICP ICP ICP ICP 09H Register Address[15:0] ("0FH" for all Flash Ctrl Regs) Register Address[7:0] Size[7:0] 1-256 data bytes * Write Flash Memory (0AH)--The Write Flash Memory command is used to write data to the main memory area or Information Area of the Flash memory. The command has equivalent functionality to the CPU writing the memory through the LDC and LDCI instructions. Data can be written 1 to memsize bytes at a time where memsize represents the size (32 KB or 64 KB) of the Flash memory for the product option chosen (The memsize number of bytes can be written by setting the size to 0). Should a size value greater than the maximum memory size be given by the user, the actual size value 19-4572; Rev 0; 4/09 ICP In-Circuit Programming Commands ZLF645 Series Flash MCUs Product Specification 60 for the command will default to the maximum memory size. The on-chip Flash Controller must be written to and unlocked for the programming operation to occur. If the Flash Controller is not unlocked, the data is discarded. Also, data is discarded for writes to protected areas of the Flash's main or information Page 3 areas based upon the settings of the read/write protect option bits in User Option Byte 1 (OPT1) register. ICP ICP ICP ICP ICP ICP 0AH Flash Memory Address[15:8] Flash Memory Address[7:0] Size[15:8] Size[7:0] 1-memsize data bytes * Read Flash Memory (0BH)--The Read Flash Memory command is used to read data from the Flash's main memory area or Information Area. This command is equivalent to the CPU reading the memory through the LDC and LDCI instructions. Data can be read 1 to `memsize' bytes at a time where memsize represents the size (32 KB or 64 KB) of the Flash memory for the product option chosen (The memsize number of bytes can be written by setting the size to 0). Depending on the settings of the read/write protect option bits in User Option Byte 1 register, reads to protected areas of the Flash's main memory area will return FFH for the data. ICP ICP ICP ICP ICP ICP 0BH Flash Memory Address[15:8] Flash Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes * Read Flash Main Memory CRC (0EH)--The Read Flash Main Memory CRC command computes and returns the Cyclic Redundancy Check (CRC) of the Flash's Main Memory using the 16-bit CRC-CCITT polynomial. If the device is not in ICP mode, this command returns FFFFH for the CRC value. Unlike most other ICP Read commands, there is a delay from issuing of the command until the ICP returns the data. The ICP reads the Main Memory, calculates the CRC value, and returns the result. The delay is a function of the Flash main memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Flash main memory. ICP 0EH ICP CRC[15:8] ICP CRC[7:0] * Read ICP Autobaud Register (1BH)-- The Read ICP Autobaud register command reads the 12-bit ICP autobaud value set during autobaud detection. ICP 1BH ICP (4'b0000, Autobaud[11:8]) 19-4572; Rev 0; 4/09 ICP In-Circuit Programming Commands ZLF645 Series Flash MCUs Product Specification 61 ICP Autobaud[7:0] * Write Test Mode Register (F0H)-- The Write Test Mode Register command writes the data that follows the command to the TEST Mode Register (TESTMODE). ICP F0H ICP TESTMODE[7:0] * Read Test Mode Register (F1H)-- The Read Test Mode register command reads the value of the TESTMODE register. ICP F1H ICP TESTMODE[7:0] ICP Autobaud[7:0] Flash Programming through the ICP Interface Differences Between CPU Based and ICP Based Flash Programming/ Erase Access Following are the differences for the allowed access capabilities between Flash accesses initiated by the CPU through instruction code and those initiated through the ICP interface: 1. The settings of the Flash Controller's Sector Protect Register (SPR) are ignored for Flash programming or page erase operations initiated through the ICP interface. 2. Mass erase operations can be executed through the ICP interface. Using ICP Commands for Flash Programming/Read Operations As described in the ICP In-Circuit Programming Commands, there are two commands that can be used for Flash programming and Flash data read operations. These commands are the Write Flash Memory (0AH) and Read Flash Memory (0BH) commands. To minimize the programming time required to program the Flash Memory using the ICP interface the following considerations concerning the use of these commands should be kept in mind: * The Write Flash Memory command can be used in two different ways for transmitting Flash programming data. When 1 or more data bytes are to be programmed to one or more non-sequential Flash Memory address locations, a value of 0001H for the Size [15:8] and Size [7:0] arguments must be used. Using the command in this way requires that, for each byte of data to be programmed, 6 bytes be transmitted across the ICP. Following is an example of the ICP transmit sequence using the command, for programming two bytes of data: 19-4572; Rev 0; 4/09 Flash Programming through the ICP Interface ZLF645 Series Flash MCUs Product Specification 62 ICP ICP ICP ICP ICP ICP ICP ICP ICP ICP ICP ICP 0AH Flash Memory Address1[15:8] Flash Memory Address1[7:0] 00H 01H Byte1[7:0] 0AH Flash Memory Address2[15:8] Flash Memory Address2[7:0] 00H 01H Byte2[7:0] If multiple bytes are to be programmed into sequential address locations in the Flash Memory, the Write Flash Memory command can be used so that each byte of data to be programmed only 1 byte be transmitted across the ICP, after the initial execution of the command. This is done simply by executing the command with a `Size' value other than 0001H and providing the starting address of the Flash Memory area to be programmed. Following is an example of the ICP transmit sequence using the command, for programming 3 bytes of data to three sequential address locations of the Flash Memory: ICP ICP ICP ICP ICP ICP ICP ICP 0AH Starting Flash Memory Address[15:8] Starting Flash Memory Address[7:0] 00H 03H Byte1[7:0] Byte2[7:0] Byte3[7:0] * When using the Write Flash Memory command to program bytes of data into the Flash memory, there is no buffering of the data that takes place between the ICP interface and the Flash Memory. As a result the maximum rate at which data is programmed into the Flash Memory through the ICP interface is dependent up on how long it takes the ZLF645 to complete a Flash Memory byte programming operation, once it is initiated by the ICP. For the ZLF645, the total programming time required to program one byte of data is approximately 65 s. When the Write Flash Memory command is used to program multiple bytes of data to sequential address locations in the Flash, then the maximum baud rate for Flash programming through the ICP is calculated as follows: Max Programming Baud Rate = 1 ICP byte 10 ICP bits/byte 65 s/byte = 153.8 kbaud * If multiple non-sequential locations of the Flash Memory are to be programmed, the Write Flash Memory command can be still be used. However, as previously explained, each byte to be programmed requires 6 bytes be transmitted on the ICP interface. To keep the ICP interface data rate from limiting how quickly multiple bytes can be 19-4572; Rev 0; 4/09 Flash Programming through the ICP Interface ZLF645 Series Flash MCUs Product Specification 63 programmed in this case a higher Baud rate can be used. Considering the ZLF645's system clock is of high frequency to support higher ICP Baud rates. The Baud rate necessary to support maximum programming efficiency is calculated as follows: Max Baud Rate = 6 ICP byte 10 ICP bits/byte 65 s/byte = 922.8 kbaud * The Read Flash Memory command can be used in the same two ways as described above for the Write Flash Memory command. When using the command to read multiple bytes of data from sequential address locations within the Flash memory, every byte read requires only 1 byte be received across the ICP interface. As described for the Write Flash Memory, there is no buffering of data that takes place between the ICP interface and the Flash Memory during memory reads. This means, as described for the Write Flash Memory command, the maximum Baud rate that memory read operations can occur at is dependent upon how quickly the ZLF645 completes a Flash Memory read operation, once it is initiated by the ICP. A ZLF645 memory read operation requires two system clock cycles to complete. Considering a ZLF645 system clock period of 250 ns, the theoretical maximum Baud rate reduces to the maximum Baud rate supported by the devices system clock frequency, which is calculated as follows: Max Baud Rate = 1 500 ns bit = 2 Mbaud The ICP baud rate for read operations is significantly higher than for programming operations. 19-4572; Rev 0; 4/09 Flash Programming through the ICP Interface ZLF645 Series Flash MCUs Product Specification 64 In-Circuit Programming Control Register Definitions ICP Control Register The ICP Control register (see Table 29) controls the state of the ICP interface. This register is used to enter or exit FLASH CONTROL mode. Table 29. ICP Control Register (ICPCTL) Bits Field Reset R/W 7 6 5 4 3 2 1 0 FLASHCTL 0 R/W 0 R 0 R/W 0 R Reserved 0 R 0 R 0 R 0 R Bit Position Value Description FLASH CONTROL Mode When this bit is programmed to 1, the device enters FLASH CONTROL mode. When programmed to 1, this bit enables the ICP to perform Flash memory accesses through the devices Flash Controller. FLASHCTL [7] 0 1 [6:0] -- The device is operating in NORMAL mode. The device is in FLASH CONTROL mode. Reserved--Must be written to 1. 19-4572; Rev 0; 4/09 In-Circuit Programming Control Register Definitions ZLF645 Series Flash MCUs Product Specification 65 ICP Status Register The ICP Status register (see Table 30) reports status information about the current state of the ICP and the device. Table 30. ICP Status Register (ICPSTAT) Bits Field Reset R/W 7 6 5 4 3 2 1 0 FLASHCTL FLPROT1 0 R 0 R FLRWP 0 R Reserved 0 R FLWAIT 0 R 0 R Reserved 0 R 0 R Bit Position Value Description FLASHCTL--When read, this bit indicates whether the device is in FLASH CONTROL mode. The device is operating in NORMAL mode. The device is in FLASH CONTROL mode. FLPROT1--When read, this bit indicates the value of the devices FLPROT1 option bit as read from the User Option Byte 1 Shadow Register (OPT1SR) on page 175. FLPROT1 mode is enabled. FLPROT1 mode is disabled. FLRWP--When read, this bit indicates the value of the devices FLRWP option bit as read from the User Option Byte 1 shadow register. FLRWP mode is enabled. FLRWP mode is disabled. Reserved--Must be written to 1. FLWAIT--When read, this bit indicates whether an ICP initiated Flash program, page erase, or mass erase operation is completed or not. An initiated Flash programming, page erase, or mass erase operation is now complete. A Flash programming, page erase, or mass erase operation is still in progress and has not yet completed. No new Flash operations must be started until this bit reads as a 0. Reserved--Must be written to 1. [7] 0 1 [6] 1 [5] 0 0 1 [4] [3] 0 1 -- [2:0] -- 19-4572; Rev 0; 4/09 In-Circuit Programming Control Register Definitions ZLF645 Series Flash MCUs Product Specification 66 TEST Mode Register The TEST Mode register is used to enable various device test or Flash memory access modes. At present this register only provides configuration for a single mode where, once programmed, Flash memory accesses bypass the devices Flash Controller and are done through the devices I/O pins. A complete description of this mode is available in the Flash Byte Programming Interface section. This register can only be read or written using the ICP Read/Write Test Mode Register commands. Table 31. TEST Mode Register (TESTMODE) Bits Field Reset R/W 7 6 5 4 3 2 1 0 Reserved F 0 R/W 0 R 0 R 0 R 0 R lash Controller Bypass Mode 0 R/W 0 R Reserved 0 R Bit Position Value Description Reserved-- Must be written to 1. Reads return 0. Flash Controller Bypass Mode The device is not in Flash Controller Bypass Mode. The device is in Flash Controller Bypass mode. Reserved--Must be written to 1. Reads return 0. [7:3] [2] -- 1 [1:0] 0 -- Exiting ICP Mode The ZLF645 MCU is taken out of ICP mode under any of the following conditions: * * Initiating a POR with P36 held High during the entire reset period. Lowering VDD until the ZLF645 MCU reaches a Voltage Brownout reset state. 19-4572; Rev 0; 4/09 Exiting ICP Mode ZLF645 Series Flash MCUs Product Specification 67 Flash Controller Flash Memory Overview The ZLF645 products feature either 32 KB or 64 KB of non-volatile Flash memory with read/write/erase capability. The Flash memory provides a 16-bit data interface but supports both 16-bit and 8-bit programming and read operations. The Flash memory can be programmed, read, or erased by the Flash Controller directed by either the CPU through user code or through the In-Circuit Programmer (ICP) interface pin with the ZLF645 in ICP mode. All user code or ICP Flash Accesses use the Flash's byte access mode where programs and reads occur 8 bits at a time. A Flash Byte Programming interface, as described in the section Flash Byte Programming Interface on page 82, is also available for Flash accesses through the devices GPIO pins and bypassing the Flash Controller. When the Flash Byte Programming interface is used, Flash programming and reads can be done either 8-bits or 16-bits at a time, depending on the package type of the device. The Flash memory consists of two blocks, the Main Memory and the Information Block. The Flash main memory is arranged in pages with 512 bytes per page. Flash erasures are not allowed on a byte/word basis and a 512-byte page is the minimum Flash block size that can be erased. Each page is divided into 8 rows of 64 bytes. Note: The term `page' in the context of the Flash Controller is not equivalent to the Z8(R) LXMC CPU architecture's Program Memory page. For Flash contents protection, the Flash main memory is also divided into sectors, each sector containing 16 consecutive pages. In addition to the Flash main memory, there is a 256-byte Information block, arranged as 4 rows of 64 bytes. Each row is defined as a page. User access is only allowed to Page 3, where user definable Option bits reside. Pages 2-0 are for Maxim(R) internal use. Note: Information block does not have a Flash contents sector protection mechanism. Table 32 lists the Flash main memory configuration for each device in the family of ZLF645 products. The size and configuration of the Information block is the same for all devices. Figure 19 displays the Flash memory arrangement. Table 32. ZLF645 Products Flash Memory Configurations Flash Size KBytes Flash Pages Program Memory Addresses Flash Sector Size Part Number ZLF645xxxxx32 ZLF645xxxxx64 32 KB 64 KB 64 128 0000H-7FFFH 0000H-FFFFH 8 KB 8 KB 19-4572; Rev 0; 4/09 Flash Controller ZLF645 Series Flash MCUs Product Specification 68 Up to 64 KB Flash Main Program Memory Sector 7 Sector 6 Sector 5 256 B Flash Information Memory Addresses (hex) Addresses (hex) 00FF FFFF Page 3 00C0 00BF E000 Page 2 DFFF 0080 4 Pages 007F For Maxim 64 Bytes each C000 Internal Use Page 1 0400 BFFF 003F Page 0 A000 0000 9FFF 8000 7FFF 6000 5FFF 4000 Sector 4 Up to 8 Sectors 16 512-Byte Pages per Sector Sector 3 Sector 2 Sector 1 3FFF 2000 1FFF 0000 Sector 0 Figure 19. Flash Memory Arrangement Flash Information Block The Flash Information Block of Flash memory is divided into two sections. Page 3 of the Information Block is accessible by you or Flash programmer vendor for programming, reading, or erasure through the ZLF645's ICP interface or it's Flash Byte Programming Interface only, as described in the section Flash Byte Programming Interface on page 82. The CPU has no access to this area of memory. User Option Bytes 0 and 1 use addresses 00FE and 00FF respectively of the Page 3 area and contain programmable bits with pre-defined functions. The Flash read/write protect bits in User Option Byte 1 control the level of Page 3 access allowed to you along with the User's level of access to the Flash's main memory. Bytes 00C0 through 00FD of Page 3 have no pre-defined function and are available to you for other operations. 19-4572; Rev 0; 4/09 Flash Memory Overview ZLF645 Series Flash MCUs Product Specification 69 Pages 0 through 2 (addresses 0000 through 00BF), of the Information Area are reserved for Maxim(R) internal use and are inaccessible by you or programmer vendor, either through the ICP interface or by using the Flash Byte Programming interface. Flash Controller Overview The Flash Controller provides the appropriate Flash controls and timing for byte/word programming, Page Erase, Mass Erase, and reading of the Flash memory for Flash accesses made by either the CPU or through the ICP interface. It also limits programming, erase, and read access to the Flash memory based upon certain register and/or option bit settings. External accesses through the ZLF645's ICP or Flash Byte Programming Interfaces are limited by the Flash Controller based upon the programming of the ZLF645's Flash read/write protect bits in User Option Byte 1. Accesses by the CPU during code execution is limited based upon the programming of the Flash Controller's Sector Protect (FSEC) registers. All Flash memory accesses through the Flash Controller are prevented unless the Flash Controller is in `unlocked' state. Executing Flash Memory Accesses Through the Flash Controller Flash Access Timing Control Programming Requirements Before a program or erase operation can be executed by the Flash Controller on the Flash memory, you must first configure the Flash Controller's Flash frequency High and Low Byte registers. These registers combine to form a 16-bit value (FFREQ) that is used by the Flash Controller to control timing for Flash program and erase operations. For proper timing, the 16-bit binary Flash Frequency value must be programmed with the system clock frequency (in kHz). This 16-bit binary Flash Frequency value is calculated using the following equation: System Clock Frequency (Hz) FFREQ[15:0] = -----------------------------------------------------------------------------1000 Using a 16-bit value FFREQ value, the Flash Controller is able to provide correct program and erase operation timing across a CPU clock frequency range of 1 MHz to 8 MHz. Caution: The System Clock Frequency depends on the Flash memory programming of bit 2 of the User Option Byte 1 and on the register programming of bit 0 of the SMR register and can be equal to the clock input frequency on the XTAL1 pin, a divide by 2 of that input, a divide by 16 of that input, or a divide by 32 of that input. Flash programming and erasure are not supported for CPU clock frequencies below 1 MHz or above 8 MHz. The Flash Frequency High and Low Byte registers must be loaded with the correct values. 19-4572; Rev 0; 4/09 Flash Controller Overview ZLF645 Series Flash MCUs Product Specification 70 Enabling the Flash Controller For Flash Memory Accesses Upon ZLF645 reset, the Flash Controller is put into a `locked' state where Flash Accesses through the controller are disabled. Before any Flash memory accesses can take place through the Flash Controller it must be `unlocked'. This functionality is designed to help protect against accidental programming or erasure of the Flash memory by Flash accesses initiated by the ICP interface or by the CPU during code execution. To `unlock' the Flash Controller the ICP or CPU must perform the following sequence of Flash Controller Register write operations: 1. Program the Flash Controller's Page Select (PGS) register with the page to be programmed or erased. 2. Program the Flash Controller's Flash Control Register (FCTL) with a value of 73H. 3. Program the Flash Controller's Flash Control Register (FCTL) with a value of 8CH. 4. Program the Flash Controller's Page Select (PGS) register with the same value as programmed in step 1 above. Failure to follow the exact register programming sequence as described above causes the Flash Controller to revert back to `locked' state and the sequence must be repeated starting from step 1. For instance, if the two Page Select register writes in steps 1 and 4 do not match, the controller reverts to `locked' state. After `unlocking' the Flash Controller, a programming or page erase operation can now be initiated through the Flash Controller to the page pointed to by the Page Select (PGS) register. For example, once the Flash Controller is `unlocked', writing a 95H to the Flash Control (FCTL) register initiates a page erase. For a description of how to execute programming, see Byte Programming on page 74. As mentioned in the Flash Memory Overview on page 67, CPU initiated programming or erase operations may be limited by the Flash Controller based upon the values programmed in the Flash Controller's Sector Protect (FSEC) register. For CPU initiated operations, the operation must be to a non-protected sector for the Flash Controller to execute the operation. For ICP initiated programming or erase operations, or if the page to be programmed/erased is in the Flash information Area, the operation is executed independent of the Sector Protect (FSEC) register settings. After unlocking a specific page, the ICP or CPU can program any byte on that page or erase that page. For programming, after a byte is written the page remains unlocked, allowing for subsequent writes to other bytes on the same page. Once `unlocked', the Flash Controller will revert to `locked' state under the following conditions: 1. The Flash Controller has completed any programming operations in progress and the ICP or CPU writes the Flash Control (FCTL) register with a value other than 95H or 63H. 2. The Flash Controller has successfully completed a page erase or mass erase operation. 19-4572; Rev 0; 4/09 Flash Controller Overview ZLF645 Series Flash MCUs Product Specification 71 3. The CPU writes to the Page Select (PGS) register. Figure 20 displays the basic Flash Controller operation considering code based CPU Flash accesses and based upon the programming of the Flash Controllers Flash Control (FCTL), Sector Protect (FSEC), and Page Select (FPS) Registers. As mentioned previously for ICP based Flash accesses, the only modification to Figure 20 is that the programming of the Sector Protect (FSEC) register is ignored and the ICP has programming and erase access to a page independent of whether it resides in a protected sector. Figure 20 does not display the effects of the Flash read/write protect bits of User Option byte 1. If either of these bits is enabled, their function takes priority over the operation description displayed in Figure 20 in terms of when a page erase or byte programming access is allowed (for more details, see Flash Code Protection Against External Access on page 73). 19-4572; Rev 0; 4/09 Flash Controller Overview ZLF645 Series Flash MCUs Product Specification 72 Reset Lock State 0 Write Page Select Register Write FCTL No 73H Yes Lock State 1 Writes to Page Select Register in Lock State 1 result in a return to Lock State 0 Write FCTL No 8CH Yes Write Page Select Register No Page Select values match? Yes Yes Page in Protected Sector? No Page Unlocked Program/Erase Enabled Byte Program Write FCTL 95H or 63H No Yes Erase Figure 20. Flash Controller Operation Flow Chart 19-4572; Rev 0; 4/09 Flash Controller Overview ZLF645 Series Flash MCUs Product Specification 73 Flash Code Protection Against External Access The Flash Controller limits Flash Access capabilities of the ICP and Flash Byte Programming Interfaces based upon the Flash read/write protect bits in User Option Byte 1. By programming these bits, you can configure the Flash Controller to block page 3 information area erasures, main memory reads, and main memory page erasures and programming as initiated through the ICP or Byte Programming Interfaces of the ZLF645. For more information, see Table 85 on page 174. Flash Code Protection Against Accidental Program and Erasure As mentioned previously, the ZLF645 products provide several levels of protection against accidental program and erasure of the Flash main memory contents by ICP and CPU accesses through the Flash Controller. Through the Flash Controller's register locking mechanism, page select redundancy, and sector level protection control, the ZLF645 products provide protection against accidental program and erasure of the Flash main memory contents by CPU and ICP accesses, except that for the ICP sector level protection is ignored. Similar levels of protection are in place for the Flash Information Area, minus the sector level protection. Sector Based Flash Protection For CPU initiated Flash main memory accesses, programming/erase protection is possible on a sector level basis through programming of the Flash Controller's Sector Protect (FSEC) register. For all ZLF645 products, each sector contains 16 pages (of 512 bytes each). Part Number Number of Sectors ZLF645xxxxx32 ZLF645xxxxx64 4 8 The Sector Protect (FSEC) register controls the protection state of each Flash sector. This register is address-shared with the Page Select register. It can only be accessed with the Flash Controller in `locked' state. With the Flash Controller in `locked' state, writing the Flash Control (FCTL) register with a value 5EH enables the Flash Controllers Sector Protect register to be written. The next write performed to Bank F, Register Address 02H then targets the Flash Controller's Sector Protect (FSEC) register. The Sector Protect register is initialized to 0 on reset, putting each sector into an unprotected state. When a bit in the Sector Protect register is written to 1, the corresponding sector within the Flash memory can no longer be programmed or erased if for operations initiated by the CPU. Operations through the ICP are unaffected by the 19-4572; Rev 0; 4/09 Flash Controller Overview ZLF645 Series Flash MCUs Product Specification 74 settings of the Sector Protect (FSEC) register. After a bit of the Sector Protect register has been set, it cannot be cleared except by powering down the device. Byte Programming All Flash accesses either through CPU code execution or through the ICP interface occur using the Flash memory byte mode of operation. The Flash Controller allows CPU programming access to the Flash's main memory area only whereas the ICP has access to both the main memory and the page 3 information area for programming. The Flash memory is enabled for byte programming by either the CPU or the ICP after unlocking the Flash Controller and executing either a Mass Erase or Page Erase operation. When the Flash Controller is unlocked and a main memory Mass Erase is executed, all Flash Main Memory locations are available for byte programming by the CPU. In contrast, when the Flash Controller is unlocked and a main memroy Page Erase is executed, only the locations of the selected page as per the Page Select (PGS) register are available for byte programming by the CPU. An erased Flash byte contains all 1's (FFH). The programming operation can only be used to change bits from 1 to 0. To change a Flash bit (or multiple bits) from 0 to 1 requires an erase operation through execution of either a Page Erase or Mass Erase command to the Flash Controller. Byte Programming can be accomplished through the ICP by using the Write Memory command or by the Z8 LXMC CPU through execution of the LDC or LDCI instructions. For a description of the LDC and LDCI instructions, refer to Z8(R) LXMC CPU User Manual (UM0215). During execution of a CPU initiated programming operation the system clock to the CPU is halted preventing further code execution, however the system clock and the on-chip peripherals continue to operate. Once the programming operation is complete, the CPU resumes code execution. To exit programming mode and lock the Flash the CPU can perform a write of any value to the Flash Control (FCTL) register, except the Mass Erase or Page Erase commands. Page Erase The Flash main memory can be erased one page (512 bytes) at a time. Page Erasing the Flash memory sets all bytes in that page to the value FFH. The Flash Page Select (PGS) register identifies the page to be erased. For CPU initiated page erase operations, only a page residing in an unprotected sector can be erased. With the Flash Controller unlocked and the active page set, writing the value 95H to the Flash Control (FCTL) register initiates the Page Erase operation. As with programming, during execution of a CPU initiated page erase operation the system clock to the CPU is halted preventing further code execution, however the system clock and the on-chip peripherals continue to operate. Once the page erase operation is complete, the CPU resumes code execution. If a Page Erase operation to the Flash's main memory is performed using the ICP, bit 3 of the ICP Status register can be polled to determine when the operation is complete. When the Page Erase is complete, the Flash Controller returns to its locked state. Although the 19-4572; Rev 0; 4/09 Flash Controller Overview ZLF645 Series Flash MCUs Product Specification 75 Flash Controller prevents CPU accesses to the Flash's Information block, the ICP can initiate a Page erase to page 3 of Information Area by a similar process as used for the main memory. The only difference is that the ICP must first write bit 7 of the Flash Page Select (PGS) register to a 1 before writing the page erase command to the Flash Control (FCTL) register. For more details, see Table 34 on page 77. Mass Erase The Flash main memory can also be Mass Erased using the Flash Controller, but only through the ICP interface and not by the CPU. Mass Erasing the Flash memory sets all bytes to the value FFH. With the Flash Controller unlocked, writing the value 63H to the Flash Control register initiates the Mass Erase operation. If a Mass Erase operation is performed using the ICP, bit 3 of the ICP Status register is polled to determine when the operation is complete. When the Mass Erase is complete, the Flash Controller returns to its locked state. You cannot mass erase the Information Area. Caution: If either of the Flash Memory Protect Option Bits are set as defined in the Flash Option Bits section, a mass erase of the Flash's main memory must be performed before Page 3 of the Flash's Information Area can be erased. These two operations must be done when the device is at operating voltage. That is, if a mass erase is followed with a power-down then power-up sequence, performing an Information Area Page 3 erase will not erase its contents. Flash Control Register Definitions Flash Control Register The Flash Controller must be unlocked using the Flash Control (FCTL) register (see Table 33) before the Flash Controller is enabled for programming or erasing the Flash memory. Writing values of 73H and then 8CH sequentially to the Flash Control register unlocks the Flash Controller, as long as the other conditions described in Enabling the Flash Controller For Flash Memory Accesses on page 70 have been met. When the Flash Controller is unlocked, a Mass Erase initiated by the ICP, or Page Erase initiated by the ICP or CPU can be executed by the Flash Controller by writing the appropriate command value to this register. Execution of a Page Erase applies only to the active page selected in Flash Page Select (FPS) register. Writing an invalid value or an invalid sequence returns the Flash Controller to its locked state. The Write-only Flash Control register shares its Register File address with the Read-only Flash Status register. 19-4572; Rev 0; 4/09 Flash Control Register Definitions ZLF645 Series Flash MCUs Product Specification 76 Table 33. Flash Control Register (FCTL) Bits Field Reset R/W Address Bit Position Value Description FCMD--Flash Command First unlock command. Second unlock command. Page Erase command (From Flash Controller `Locked' state, must be the third command written to this register to initiate Page Erase). Mass Erase command (Ignored by Flash Controller if written by the CPU and executed by Flash Controller if ICP writes the command. From Flash Controller `Locked' state, must be the third command written to this register to initiate Mass Erase). Enable Flash Sector Protect Register Access. 7 6 5 4 3 2 1 0 FCMD 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Bank F, Register address: 01H [7:0] 73H 8CH 95H 63H 5EH 19-4572; Rev 0; 4/09 Flash Control Register Definitions ZLF645 Series Flash MCUs Product Specification 77 Flash Status Register The Flash Status (FSTAT) register (see Table 34) indicates the current state of the Flash Controller. This register can be read any time. The read-only Flash Status (FSTAT) register shares its Register File address with the Write-only Flash Control (FCTL) register. Table 34. Flash Status Register (FSTAT) Bits Field Reset R/W Address Bit Position Value 7 6 5 4 3 2 1 0 Reserved 0 R 0 R 0 R 0 R 0 R FSTAT 0 R 0 R 0 R Bank F, Register address: 01H Description Reserved--Reads as 0's. FSTAT--Flash Controller Status Flash Controller locked. First unlock command received (73H written). Second unlock command received (8CH written). Flash Controller unlocked. Sector protect register selected. Program operation in progress. Page erase operation in progress. Mass erase operation in progress. [7:6] [5:0] -- 000000 000001 000010 000011 000100 001xxx 010xxx 100xxx Flash Page Select Register The Flash Page Select (FPS) register (see Table 35) shares address space with the Flash Sector Protect (FSEC) register. Unless the Flash Controller is in `locked' state and its Flash Control (FCTL) register is written with 5EH, writes to this address target the Flash Page Select (FPS) register. The FPS register is used to select one page within the Flash Main Memory or Information Block for programming or erasure depending upon whether its IFEN bit is 0 or 1 respectively. Each Flash Main Memory Page contains 512 bytes of Flash memory. During a Page Erase operation to the Main Memory, the page that will be erased is the one containing the 512 Flash memory locations where bits 15 through 9 of their addresses is equal to bits 6 through 0 of FPS register. For Main Memory programming operations, bits 15 through 9 of the address to be programmed must equal bits 6 through 0 of the FPS register for the Flash Controller to execute the operation. For page erase or programming operations to the Flash's Information Block as indicated by the IFEN bit being 1, the programming or 19-4572; Rev 0; 4/09 Flash Control Register Definitions ZLF645 Series Flash MCUs Product Specification 78 page erase command must be initiated by the ICP. Information Block page erase or programming operations initiated by the CPU are ignored by the Flash Controller. In the case of an Information Block programming or page erase operation initiated by the ICP, the FPS register must first be programmed with 83H to point to page 3 of the Information Block or else the operation will be ignored by the Flash Controller. For Information Block programming through the ICP, bits 12 through 6 of the address must equal bits 6 through 0 of the FPS register for the Flash Controller to execute the operation. Table 35. Flash Page Select Register (FPS) Bits Field Reset R/W Address Bit Position Value Description IFEN--Information Area Enable Operation to be performed on Flash main memory. Operation to be performed on Flash Information Area. PAGE--Page Select This 7-bit field identifies the Flash main memory page for Page Erase and Page unlocking. Program Memory Address[15:9] = PAGE[6:0]. The least significant 2 bits of Page identifies the Flash Information page for Page Erase and Page unlocking. The upper significant bits must be logic 0's. 7 6 5 4 3 2 1 0 IFEN 0 R/W 0 R/W 0 R/W 0 R/W PAGE 0 R/W 0 R/W 0 R/W 0 R/W Bank F, Register address: 02H [7] 0 1 0 1 [6:0] Flash Sector Protect Register The Flash Sector Protect (FSEC) register (see Table 36) address is shared with the Flash Page Select (FPS) register. It is accessed by first writing 5EH to the Flash Control (FCTL) register with the Flash Controller in `locked' state, and then writing to the register file address location given for the Flash Page Select (FPS) register. The FSEC register selects which of the eight available Flash memory sectors is to be protected from CPU initiated programming or page erase operations. For ICP initiated programming or page erase operations, the settings within the FSEC register are ignored by the Flash Controller. The reset state of each Sector Protect bit in the FSEC register is its unprotected state or 0 value. After a sector is protected by setting its corresponding register bit to 1, it cannot be unprotected (the register bit cannot be cleared) without powering down the device. 19-4572; Rev 0; 4/09 Flash Control Register Definitions ZLF645 Series Flash MCUs Product Specification 79 Table 36. Flash Sector Protect Register (FSEC) Bits Field Reset R/W Address Bit Position Value Description SPROT7-SPROT0--Sector Protection Each bit corresponds to an 16-page Flash sector. For the ZLF645xxxxx64, all bits are used. Only bits 3-0 are used in the ZLF645xxxxx32. For ICP initiated operations, no sector protection exists. 7 6 5 4 3 2 1 0 SPROT7 0 R/W SPROT6 0 R/W SPROT5 0 R/W SPROT4 0 R/W SPROT3 0 R/W SPROT2 0 R/W SPROT1 0 R/W SPROT0 0 R/W Bank F, Register address 02H [7:0] Flash Frequency High and Low Byte Registers The Flash Frequency High and Low Byte registers (Table 37 and Table 38) combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash frequency value must contain the system clock frequency (in kHz) and is calculated using the following equation: System Clock Frequency (Hz) FFREQ[15:0] = FFREQH[7:0], FFREQL[7:0] = -----------------------------------------------------------------------------1000 Programming the Flash Frequency High and Low Byte Registers as per the formula provides a Flash programming time of approximately 30 s and an erase time of approximately 10 ms. Caution: Flash programming and erasure is not supported for system clock frequencies below 1 MHz or above 8 MHz. The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure proper operation of the device. 19-4572; Rev 0; 4/09 Flash Control Register Definitions ZLF645 Series Flash MCUs Product Specification 80 Table 37. Flash Frequency High Byte Register (FFREQH) Bits Field Reset R/W Address Bit Position Value Description FFREQH--Flash Frequency High Byte High byte of the 16-bit Flash Frequency value. 7 6 5 4 3 2 1 0 FFREQH 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bank F, Register address: 03H [7:0] Table 38. Flash Frequency Low Byte Register (FFREQL) Bits Field Reset R/W Address 7 6 5 4 3 2 1 0 FFREQL 0 R/W Bank F, Register address: 04H Bit Position Value Description FFREQL--Flash Frequency Low Byte Low byte of the 16-bit Flash Frequency value. [7:0] Flash Controller Functions Summary The Flash Controller performs its functions, directed by either the ICP interface or by the CPU through instruction codes. Table 39 lists the functions that will or will not be performed by the Flash Controller, according to whether the CPU or ICP is the initiator, whether the operation is performed on the Flash's Main Memory or Information Block, and whether either of the two read/write protect bits of User Option Byte 1 have been enabled or not. 19-4572; Rev 0; 4/09 Flash Control Register Definitions ZLF645 Series Flash MCUs Product Specification 81 Table 39. Flash Controller Functions Summary Control Source Flash Memory Block Program Read Page Erase Mass Erase Flash Protect ICP Main Memory Information Area Main Memory Information Area Yes Page 3 Only Yes No Yes Page 3 Only Yes No Yes Page 3 Only Yes No Yes No No No Yes1 Yes2 No3 No3 CPU through Instruction Code Notes 1. FLPROT1 = 0, cannot read or write lowest half of memory. FLRWP = 0, cannot read or write entire main memory. 2. FLRWP/FLPROT1 = 0, cannot write or erase Page 3. 3. FLPROT1 = 0, no effect. FLRWP = 0, no effect. 19-4572; Rev 0; 4/09 Flash Control Register Definitions ZLF645 Series Flash MCUs Product Specification 82 Flash Byte Programming Interface Using the ZLF645's Flash Byte Programming interface, the on-chip Flash controller can be bypassed, allowing direct control of the Flash signals through registered values of certain of the ZLF645's GPIO pins. Bypassing the Flash controller allows faster row programming algorithms to be used by controlling the Flash programming signals directly. This method is beneficial when programming a large number of devices and can be used for Flash programming by third party vendors who manufacture gang programmers. For more information on how to use this interface, refer to Third-Party Flash Programming Support for Z8 Crimzon Flash Parts, available for download at www.maxim-ic.com. Enabling The Flash Byte Programming Interface The Flash Byte Programming Interface is enabled by writing three bytes to the ICP interface: 1. 80H -- initiates auto-baud calculation of the ICP interface data and clock rate. 2. F0H -- ICP Write Test Mode Register command. 3. 04H -- Data to be written to the Test Mode Register. This enables the Flash Byte Programming interface. Note: Since Flash Byte Programming Interface is enabled with the ZLF645 MCU in ICP mode, the CPU clock will stop and no CPU accesses to the Flash memory will occur. Flash Byte Programming Interface Flash Access Restrictions The types of Flash access allowed to the Flash memory through the Flash Byte Programming interface is qualified similar to the ICP, by the settings of the Flash Memory Protection Bits in User Option Byte 1. If either of the Flash protect bits are set, the program memory has to be mass erased before full read/program access is allowed to either the main memory or Information area page 3 sections of the Flash memory, respectively. Flash memory access allowed through the Flash Byte Programming interface is summarized in Table 40. 19-4572; Rev 0; 4/09 Flash Byte Programming Interface ZLF645 Series Flash MCUs Product Specification 83 Table 40.Flash Byte Programming Functions Summary Flash Memory Block Program Read Page Erase Mass Erase Flash Protect Option Bits Main Memory Main Memory Main Memory Information Area Information Area Information Area Yes No Yes1 Yes2 No No Yes No Yes1 Yes2 Yes2 Yes2 Yes No Yes1 Yes2 No No Yes Yes Yes Yes Yes Yes FLRWP=1, FLPROT1=1 FLRWP=0, FLPROT1=X FLRWP=1, FLPROT1=0 FLRWP=1, FLPROT1=1 FLRWP=1, FLPROT1=0 FLRWP=0, FLPROT1=1 Notes 1. Program, Read, and Page Erase access is limited to the upper half address space of the main memory only. 2. Only Page 3 of the Information Area is accessible for Program, Read, and Page Erase operations. 19-4572; Rev 0; 4/09 Flash Byte Programming Interface Flash Access Restrictions ZLF645 Series Flash MCUs Product Specification 84 Infrared Learning Amplifier The ZLF645 MCU's infrared learning amplifier allows you to detect and decode infrared transmissions directly from the output of the receiving diode without the need for external circuitry (see Port 3 on page 23). An IR diode can be connected to the IR amplifier as displayed in Figure 21. When the IR amplifier is enabled and an input current is detected on Port 3, Pin 1 (P31), the IR amplifier outputs a logical High value. When the input current is below the switching threshold of the IR amplifier, the amplifier outputs a logical Low value. Within the MCU, the IR amp output goes to the capture/timer logic, which can be programmed to demodulate the IR signal. The IR amplifier output can also be read by the CPU, or drive the Port 3, Pin 4 (P34) output if write-only register bit PCON[0] is set to 1. For the maximum current input that is clearly recognized by the ZLF645 as a 0 and the minimum current input that is clearly recognized as a 1, see IDETLO and IDETHI parameters, respectively, in Table 80 on page 165. The IR learning amplifier can demodulate signals up to a frequency of 500 kHz. A special mode exists that allows you to capture the third, fourth, and fifth edges of the IR amplifier output and generate an interrupt. VDD D1 Photodiode P31 of MCU Figure 21. Learning Amplification Circuitry within the ZLF645 Flash MCU For details on programming the timers to demodulate a received signal, see Timers on page 99. 19-4572; Rev 0; 4/09 Infrared Learning Amplifier ZLF645 Series Flash MCUs Product Specification 85 Universal Asynchronous Receiver/ Transmitter The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The two UARTs use a single 8-bit data mode with selectable parity. The UART interface when enabled uses the GPIO pins P07 for the UART transmit and P32 for the UART receive. The features of the UART include: * * * * * * * * * 8-bit asynchronous data transfer Selectable even- and odd-parity generation and checking One or two Stop bits Separate transmit and receive interrupts Framing, overrun, and break detection Separate transmit and receive enables 8-bit Baud Rate Generator Baud Rate Generator timer mode UART operational during HALT mode Table 41. UART Control Registers Address (Hex) 12-Bit Bank 8-Bit Register Description Mnemonic Reset XXh 0000_0010b 00h FFh Page No 0F1 0F2 0F3 0F4 All All All All F1 F2 F3 F4 UART Receive/Transmit Data Register UART Status Register UART Control Register UART Baud Rate Generator Constant Register URDATA/ UTDATA UST UCTL BCNST 95 95 97 98 19-4572; Rev 0; 4/09 Universal Asynchronous Receiver/Transmitter ZLF645 Series Flash MCUs Product Specification 86 Architecture The UARTs consist of three primary functional blocks: transmitter, receiver, and Baud Rate Generator. The UART transmitter and receiver function independently, but employ the same baud rate and data format. Figure 22 displays the UART architecture. RxD Receive Shifter Receive Data Register System Bus Control Register Transmit Data Register Status Register Baud Rate Generator TxD Transmit Shift Register Transmitter Control Parity Generator Figure 22. UART Block Diagram Operation The UART channel can be used to communicate with a master microprocessor or a slave microprocessor, both of which exhibit transmit and receive functionality. You can either operate the UART channel by polling the UART Status register or via interrupts. The UART remains active during HALT mode. If neither the transmitter nor the receiver is enabled, the UART baud rate generator can be used as an additional timer. The UART contains a noise filter for the receiver that can be enabled by the user. 19-4572; Rev 0; 4/09 Architecture ZLF645 Series Flash MCUs Product Specification 87 Data Format The UART transmits and receives data in an 8-bit data format, with the least significant bit (lsb) occurring first. An even- or odd-parity bit can be optionally added to the data stream. Each character begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits. Figure 23 and Figure 24 display the asynchronous data format employed by the UARTs with or without parity, respectively. Idle state of line Start 0 Data field LSB Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 1 2 Stop bit(s) 1 Figure 23. UART Asynchronous Data Format without Parity 1 0 Idle state of line Start Data field LSB Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 MSB Bit 7 1 2 Stop bit(s) Figure 24. UART Asynchronous Data Format with Parity Transmitting Data Using Polled Method Follow the steps below to transmit data using the polled method of operation: 1. Write to the Baud Rate Generator Constant (BCNST) register, address 0F4h, to set the appropriate baud rate. 2. Write 0 to bit 6 of the P01M register. 3. Write to the UART Control register (UCTL) to: (a) Set the transmit enable bit, UCTL[7], to enable the UART for data transmission. (b) If parity is appropriate, set the parity enable bit, UCTL[4] to 1 and select either even- or odd-parity (UCTL[3]). 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 88 4. Check the Transmit Status register bit, UST[2], to determine if the Transmit Data register is empty (indicated by 1). If empty, continue to Step 6. If the Transmit Data register is full (indicated by 0), continue to monitor the UST[2] bit until the Transmit Data register is available to receive new data. 5. Write the data byte to the UART Transmit Data register, 0F1h. The transmitter automatically transfers the data to the internal transmit shift register and transmits the data. 6. To transmit additional bytes, return to Step 4. 7. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all data in the Transmit Data and internal shift registers has been transmitted. Caution: Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted. Data written while the transmit data status bit is clear (UST[2]=0) overwrites the previous value written, so the previous written value will not be transmitted. Disabling the UART transmitter while the transmit completion status bit is clear (UST[1]=0) can corrupt the byte being transmitted. Transmitting Data Using Interrupt-Driven Method The UART transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission. Follow the steps below to configure the UART for interrupt-driven data transmission: 1. Write to the BCNST register to set the appropriate baud rate. 2. Write 0 to bit 6 of the P01M register. 3. Execute DI instruction to disable interrupts. 4. Write to the Interrupt Control registers to enable the UART Transmitter interrupt and set the appropriate priority. 5. Write to the UART Control register to: (a) Set the transmit enable bit (UCTL bit 7) to enable the UART for data transmission. (b) Enable parity, if appropriate, and select either even- or odd-parity. 6. Execute an EI instruction to enable interrupts as the transmit buffer is empty, an interrupt is immediately executed. 7. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Internal Transmit Shift register and transmits the data. 8. Execute the IRET instruction to return from the interrupt service routine (ISR) and wait for the Transmit Data register to again become empty. 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 89 9. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all data in the Transmit Data and Internal Shift registers has been transmitted. Caution: Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted. Data written while the transmit data status bit is clear (UST[2]=0) overwrites the previous value written, so the previous written value will not be transmitted. Disabling the UART transmitter while the transmit completion status bit is clear (UST[1]=0) can corrupt the byte being transmitted. Receiving Data Using the Polled Method Follow the steps below to configure the UART for polled data reception: 1. Write to the BCNST register to set the appropriate baud rate. 2. Write to the UART Control register (UCTL) to: (a) Set the receive enable bit (UCTL[6]) to enable the UART for data reception (b) Enable parity (if appropriate) and select either even- or odd-parity 3. Check the receive status bit in the UART Status register, bit UST[7], to determine if the Receive Data register contains a valid data byte (indicated by a 1). If UST[7] is set to 1 to indicate available data, continue to Step 4. If the Receive Data register is empty (indicated by a 0), continue to monitor the UST[7] bit awaiting reception of the valid data. 4. Read data from the UART Receive Data register. 5. Return to Step 3 to receive additional data. Receiving Data Using the Interrupt-Driven Method The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow the steps below to configure the UART receiver for interrupt-driven operation: 1. Write to the UART BRG Constant registers to set the appropriate baud rate. 2. Execute DI instruction to disable interrupts. 3. Write to the Interrupt Control registers to enable the UART receiver interrupt and set the appropriate priority. 4. Clear the UART Receiver interrupt in the applicable Interrupt Request register. 5. Write to the UART Control register (UCTL) to: (a) Set the receive enable bit (UCTL[6]) to enable the UART for data reception (b) Enable parity, if appropriate, and select either even- or odd-parity 6. Execute an EI instruction to enable interrupts. 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 90 The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated ISR performs the following: 1. Checks the UART Status register to determine the source of the interrupt, whether it is an error, break, or received data. 2. Reads the data from the UART Receive Data register, if the interrupt was caused by data available. 3. Clears the UART receiver interrupt in the applicable Interrupt Request register. 4. Executes the IRET instruction to return from the ISR and await more data. UART Interrupts The UART features separate interrupts for the transmitter and the receiver. In addition, when the UART primary functionality is disabled, the BRG can also function as a basic timer with interrupt capability. Note: When the UART is set to run at higher baud rates, the UART receiver's service routine may not have enough time to read and manipulate all bits in the UART Status register (especially bits generating error conditions) for a received byte before the next byte is received. You can devise your own hand-shaking protocol to prevent the transmitter from transmitting more data while current data is being serviced. Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Status bit, UST[2], is set to 1. This indicates that the transmitter is ready to accept new data for transmission. The Transmit Status interrupt occurs after the internal transmit shift register has shifted the first bit of data out. At this point, the Transmit Data register can be written with the next character to send. This provides 7 bit periods of latency to load the Transmit Data register before the transmit shift register completes shifting the current character. Writing to the UART Transmit Data register clears the UST[2] bit to 0. The interrupt is cleared by writing a 0 to the Transmit Data register. Receiver Interrupts The receiver generates an interrupt when any of the following occurs: * A data byte is received and available in the UART Receive Data register--This interrupt can be disabled independent of the other receiver interrupt sources. The received data interrupt occurs once the receive character has been received and placed in the Receive Data register. Software must respond to this received data available condition before the next character is completely received to avoid an overrun error. The interrupt is cleared by reading from the UART Receive Data register. A break is received--A break is detected when a 0 is sent to the receiver for the full byte plus the parity and stop bits. After a break is detected, it will interrupt * 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 91 immediately if there is no valid data in the Receive Data register. If data is present in the Receive Data register, an interrupt will occur after the UART Receive Data register is read. * An overrun is detected--An overrun occurs when a byte of data is received while there is valid data in the UART Receive Data register that has not been read by the user. The interrupt will be generated when the user reads the UART Receive Data register. The interrupt is cleared by reading the UART Receive Data register. When an overrun error occurs, the additional data byte will not overwrite the data currently stored in the UART Receive Data register. A data framing error is detected--A data framing error is detected when the first stop bit is 0 instead of 1. When configured for 2 stop bits, a data framing error is only detected when the first stop bit is 0. A framing error interrupt is generated when the framing error is detected. Reading the UART Receive Data register clears the interrupt. * Note: Ensure that the transmitter uses the same stop bit configuration as the receiver. UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data register. The Break Detect and Overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the UART Status (UST) register is updated to indicate the overrun condition (and Break Detect, if applicable). The UST[7] bit is set to 1 to indicate that the Receive Data register contains a data byte. However, because the overrun error occurred, this byte may not contain valid data and must be ignored. The Break Detect bit, UST[3], indicates if the overrun was caused by a break condition on the line. After reading the status byte indicating an overrun error, the Receive Data register must be read again to clear the error bits is the UART Status 0 register. Updates to the Receive Data register occur only when the next data word is received. UART Data and Error Handling Procedure Figure 25 on page 92 displays the recommended procedure for use in UART receiver interrupt service routine. 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 92 Receiver Ready Receiver Interrupt Read Status No Errors? Yes Read Data that clears the RDA bit and resets the error bits Read Data Discard Data Figure 25. UART Receiver Interrupt Service Routine Flow 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 93 Baud Rate Generator Interrupts If the BRG interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This action allows the BRG to function as an additional counter if the UART functionality is not employed. UART Baud Rate Generator The UART Baud Rate Generator creates a lower frequency baud rate clock for data transmission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate Constant register contains an 8-bit baud rate divisor value (BCNST[7:0]) that sets the data transmission rate (baud rate) of the UART. For programmed register values other than 00h, the UART data rate is calculated using the below equation: UART Data Rate (bps) = System Clock Frequency (Hz) 16 x UART Baud Rate Divisor Value (BCNST) When the UART Baud Rate Low register is programmed to 00h, the UART data rate is calculated as follows: UART Data Rate (bps) = System Clock Frequency (Hz) 4096 When the UART Baud Rate Generator is used as a general-purpose counter, the counters time-out period can be computed as follows based upon the counters clock input being a divide by 16 of the system clock and the maximum count value being 255: 16 x UART Baud Rate Divisor Value (BCNST) System Clock Frequency (MHz) Time-Out Period (us) = Note: The relationship between the XTAL1 clock frequency and the system clock frequency must be considered before making this computation and is dependent upon the programming of bit 2 of User Option Byte 1 as well as the programming of bit 0 of the SMR register. Depending on the programmed values, the system clock frequency can be a divide by 1, a divide by 2, or a divide by 16 of the XTAL1 clock. When the UART is disabled, the BRG can function as a basic 8-bit timer with interrupt on time-out. 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 94 Follow the steps below to configure the BRG as a timer with interrupt on time-out: 1. Disable the UART by clearing the receive and transmit enable bits, UCTL[7:6] to 0. 2. Load the appropriate 8-bit count value into the UART Baud Rate Generator Constant register. The count frequency is the system clock frequency (in Hz) divided by 16. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the Baud Rate Generator bit (UCTL bit 0) in the UART Control register to 1. When configured as an 8-bit timer, the count value, instead of the reload value, is read, and the counter begins counting down from its initial programmed value. On timing out (reaching a value of 1), if the time-out interrupt is enabled, an interrupt will be produced. The counter will then reload its programmed start value and begin counting down again. Table 42 lists a number of BCNST register settings at various baud rates and system clock frequencies. Table 42. BCNST Register Settings Examples Target UART Data Rate (baud) System Clock = 4 MHz, Crystal Clock = 8 MHz System Clock = 3 MHz, Crystal Clock = 6 MHz 2400 4800 9600 19200 BCNST = 01101000 Actual baud rate = 2403 BCNST = 00110100 Actual baud rate = 4807 BCNST = 00011010 Actual baud rate = 9615 BCNST = 00001101 Actual baud rate = 19230 BCNST = 01001110 Actual baud rate = 2403 BCNST = 00100111 Actual baud rate = 4807 BCNST = 00010100 Actual baud rate = 9375 BCNST = 00001010 Actual baud rate = 18750 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 95 UART Receive Data Register/UART Transmit Data Register The UART Receive/Transmit Data register (see Table 43) is used to send and retrieve data from the UART channel. When the UART receives a data byte, it can be read from this register. The UART receive interrupt is cleared when this register is used. Data written to this register is transmitted by the UART. Table 43. UART Receive/Transmit Data Register (URDATA/UTDATA) Bit Field Reset R/W Address Bit Position Description UART Receive/Transmit When read, returns received data. When written, transmits written data. 7 6 5 4 3 2 1 0 UART Receive/Transmit X R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W Bank Independent: F1h; Linear: 0F1h [7:0] UART Status Register The UART Status register (see Table 44) displays the status of the UART. Bits [6:3] are cleared by reading the UART Receive/Transmit register (F1h). Table 44. UART Status Register (UST) Bit Field Reset R/W Address Bit Position Value Description Receive Status--Set when data is received; cleared when URDATA is read. UART Receive Data register empty. UART Receive Data register full. 7 6 5 4 3 2 1 0 Receive Status 0 R/W Parity Error 0 R/W Overrun Error 0 R/W Framing Error 0 R/W Break 0 R/W Transmit Data 0 R/W Transmit Complete 1 R/W Noise Filter 0 R/W Bank Independent: F2h; Linear: 0F2h [7] 0 1 19-4572; Rev 0; 4/09 UART Receive Data Register/UART Transmit Data ZLF645 Series Flash MCUs Product Specification 96 Bit Position Value Description Parity Error--Set when a parity error occurs; cleared when URDATA is read. No parity error occurs. Parity error occurs. Overrun Error--Set when an overrun error occurs; cleared when URDATA is read. No overrun error occurs. Overrun error occurs. Framing Error--Set when a framing error occurs; cleared when URDATA is read. No framing error occurs. Framing error occurs. Break--Set when a break is detected; cleared when URDATA is read. No break occurs. Break occurs. Transmit Data Status--Set when the UART is ready to transmit; cleared when TRDATA is written. Do not write to the UART Transmit Data register. UART Transmit Data register ready to receive additional data. Transmit Completion Status Data is currently transmitting. Transmission is complete. Noise Filter--Detects noise during data reception. No noise detected. Noise detected. [6] 0 1 [5] 0 1 [4] 0 1 [3] 0 1 [2] 0 1 [1] 0 1 Read 0 1 Write 0 1 [0] Turn off noise filter. Turn on noise filter. UART Control Register The UART Control register controls the UART. In addition to setting bit 5, you must also set appropriate bit in the Interrupt Mask register (see Table 65 on page 133). Note: This register is not reset after a Stop Mode Recovery. 19-4572; Rev 0; 4/09 UART Control Register ZLF645 Series Flash MCUs Product Specification 97 Table 45. UART Control Register (UCTL) Bit 7 6 5 4 3 2 1 0 Transmitter Receiver Enable Enable Field Reset R/W Address Bit Position Value UART Interrupts Enable 0 R/W Parity Enable 0 R/W Parity Select 0 R/W Send Break 0 R/W Stop Bits Baud Rate Generator 0 R/W 0 R/W 0 R/W 0 R/W Bank Independent: F3h; Linear: 0F3h Description [7] [6] [5] [4] [3] [2] [1] [0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Transmitter disabled. Transmitter enabled. Receiver disabled. Receiver enabled. UART Interrupts disabled. UART Interrupts enabled. Parity disabled. Parity enabled. Even parity selected. Odd parity selected. No break is sent. Send Break (force Tx output to 0). One stop bit. Two stop bits. Baud Rate Generator--When the transmitter and receiver are disabled, the BRG can be used as an additional timer. When setting this bit, clear bits [7:6] in this register. Also set bit [5] if an interrupt is required when the BRG is reloaded. BRG used as Baud Rate Generator for UART. BRG used as timer. 0 1 UART Baud Rate Generator Constant Register The UART baud rate generator determines the frequency at which UART data is received and transmitted. This baud rate is determined by the following equation: UART Data Rate (bps) = System Clock Frequency (Hz) 16 x UART Baud Rate Divisor Value (BCNST) 19-4572; Rev 0; 4/09 UART Baud Rate Generator Constant Register ZLF645 Series Flash MCUs Product Specification 98 The system clock is usually the crystal clock divided by 2. When the UART baud rate generator is used as an additional timer, a Read from this register returns the actual value of the count of the BRG in progress and not the reload value. See Table 46. Note: This register is not reset after a Stop Mode Recovery. Table 46. UART Baud Rate Generator Constant Register (BCNST) Bit Field Reset R/W Address Bit Position Description Baud Rate Generator Constant When read, returns the actual timer count value (when UCTL[0]=1). When written, sets the Baud Rate Generator Constant. The actual baud rate frequency = XTAL / (32 x BCNST). 7 6 5 4 3 2 1 0 Baud Rate Generator Constant 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bank Independent: F4h; Linear: 0F4h [7:0] 19-4572; Rev 0; 4/09 UART Baud Rate Generator Constant Register ZLF645 Series Flash MCUs Product Specification 99 Timers The ZLF645 MCU infrared timer features a 16-bit and an 8-bit counter/timer, each of which can be used simultaneously for transmitting. Both timers can be used for demodulating an input carrier wave and share a single input pin. Figure 26 displays the counter/timer architecture, which is designed to help unburden the program from coping with real-time problems like generating complex waveforms or receiving and demodulating complex waveforms and pulses. In addition to the 16-bit and 8-bit timers, the UART's baud rate generator can be used as an additional 8-bit timer when the UART receiver is not in use (for more details, see Universal Asynchronous Receiver/Transmitter on page 85). HI16 8 LO16 8 16-Bit Timer 16 Timer 16 1 2 4 8 8 16 8 SCLK Clock Divider TC16H TC16L AND/OR Logic Timer 8/16 HI8 LO8 8 8 Glitch Filter Edge Detect Circuit 8-Bit Timer 8 Timer 8 8 8 TC8H TC8L Figure 26. Counter/Timers Block Diagram 19-4572; Rev 0; 4/09 Timers ZLF645 Series Flash MCUs Product Specification 100 Table 47 summarizes the timer control registers. Some timer functions can also be affected by control registers for other peripheral functions. Table 47. Timer Control Registers Address (Hex) 12-Bit Bank 8-Bit Register Description Mnemonic Reset 0000_00 0 0 b 0000_00 0 0 b 0000_00 0 0 b 0000_0XXXb 00h 00h 00h 00h 00h 00h 00h 00h Page No D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D0A D0B D D D D D D D D D D D D 00 01 02 03 04 05 06 07 08 09 0A 0B Counter/Timer 8 Control Register Timer 8 and Timer 16 Common Functions Counter/Timer 16 Control Register Timer 8/Timer 16 Control Register Counter/Timer 8 Low Hold Register Counter/Timer 8 High Hold Register Counter/Timer 16 Low Hold Register Counter/Timer 16 High Hold Register Timer 16 Capture Low Register Timer 16 Capture High Register Timer 8 Capture Low Register Timer 8 Capture High Register CTR0 CTR1 CTR2 CTR3 TC8L TC8H TC16L TC16H LO16 HI16 LO8 HI8 119 121 124 126 118 117 117 116 116 115 115 114 Counter/Timer Functional Blocks The ZLF645 MCU infrared timer contains a glitch filter for removing noise from the input when demodulating an input carrier. Each timer features its own demodulating mode and can be simultaneously used to generate a signal output. The T8 timer has the ability to capture only one cycle of a carrier wave of a high-frequency waveform. Input Circuit Depending on the setting of register bits P3M[2:1] and CTR1[6], the timer/counter input circuit monitors one of the following conditions: * * * * The P31 digital signal, if CTR1[6]=0 and P3M[2:1]=00. The P31 analog comparator output, if CTR1[6]=0 and P3M[2:1]=01. The P31 IR amplifier output, if CTR1[6]=0 and P3M[2]=1. The P20 digital signal, if CTR1[6]=1. 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 101 Based on register bits CTR1[5:4], a pulse is generated at when a rising edge, falling edge, or any edge is detected. Glitches in the input signal are filtered out if they are shorter than the glitch filter width specified in register bits CTR1[3:2]. Figure 27 displays the input circuit. P3M[1] P31 + Comp. - + IR Amp. - 0 P3M[2] 0 1 CTR1[6] CTR1[3:2] Glitch Filter 00 4 SCLK 1 8 SCLK Reserved 01 10 11 00 10 01 11 Reserved CTR1[5:4] Edge Detection 0 Falling Edge Rising Edge CTR1[0] CTR1[1] P30 1 IREF P20 Figure 27. Counter/Timer Input Circuit The timers can be configured to operate in following modes: * * * * * T8 TRANSMIT Mode T8 DEMODULATION Mode T16 TRANSMIT Mode T16 DEMODULATION Mode PING-PONG Mode T8 TRANSMIT Mode Before T8 is enabled, the output of T8 depends on CTR1, bit 1. If the bit is 0, T8_OUT is 1; if it is 1, T8_OUT is 0. See Figure 28. 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 102 T8 (8-Bit) TRANSMIT Mode No T8_Enable Bit Set CTR0, bit 7 Yes Reset T8_ENABLE Bit 0 CTR1, bit 1 Value 1 Load TC8L Reset T8_OUT Load TC8H Set T8_OUT Set Time-Out Status Bit (CTR0 bit 5) and generate TIMEOUT_INT if enabled Enable T8 No T8_TIMEOUT Yes Single Pass Yes Single Pass? Modulo-N No 0 T8_OUT Value 1 Load TC8L Reset T8_OUT Load TC8H Set T8_OUT Enable T8 Set Time-Out Status Bit (CTR0, bit 5) and generate TIMEOUT_INT if enabled No T8_TIMEOUT Yes Figure 28. TRANSMIT Mode Flowchart 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 103 When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, bit 1). If the initial value (CTR1, bit 1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter. In SINGLE-PASS mode (CTR0, bit 6), T8 counts down to 0 and stops, T8_OUT toggles, the time-out status bit (CTR0, bit 5) is set, and a time-out interrupt can be generated if it is enabled (CTR0, bit 1). In MODULO-N mode, on reaching terminal count, T8_OUT is toggled, but no interrupt is generated. From that point, T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles T8_OUT, and sets the time-out status bit (CTR0, bit 5), thereby generating an interrupt if enabled (CTR0, bit 1). One cycle is thus completed. T8 then loads from TC8H or TC8L according to the T8_OUT level and repeats the cycle. See Figure 29. Z8 LXMC Data Bus CTR0 data bit 2 Positive Edge Negative Edge HI8 LO8 IRQ4 CTR0 data bits [4:3] Clock 8-Bit Counter T8 (TC8) CTR0 data bit 1 Clock Select SCLK T8_OUT TC8H Z8 LXMC Data Bus TC8L Figure 29. 8-Bit Counter/Timer Circuits You can modify the values in TC8H or TC8L at any time. The new values take effect when they are loaded. Caution: An initial count of 1 is not allowed (a non-function occurs). An initial count of 0 causes TC8 to count from 0 to FFh to FEh. 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 104 Notes: 1. The "h" suffix denotes hexadecimal values. 2. Transition from 0 to FFh is not a time-out condition. Caution: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended. Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must be reset. These commands are required as it takes one counter/ timer clock interval for the initiated event to actually occur. See Figure 30 and Figure 31. TC8H Counts Counter Enable command; T8_OUT switches to its initial value (CTR1 data bit 1) T8_OUT toggles; time-out interrupt Figure 30. T8_OUT in SINGLE-PASS Mode T8_OUT toggles T8_OUT TC8L TC8H TC8L TC8H TC8L Counter Enable command; T8_OUT, switches to its initial value (CTR1 data bit 1) Time-out interrupt Time-out interrupt Figure 31. T8_OUT in MODULO-N Mode 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 105 T8 DEMODULATION Mode You must program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1 bits [5:4]) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1 bits [5:4]) is detected during counting, the current value of T8 is complemented and put into one of the capture registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put into HI8. From that point, one of the edge detect status bits (CTR1, bits [1:0]) is set, and an interrupt can be generated if enabled (CTR0, bit 2). Meanwhile, T8 is loaded with FFh and starts counting again. If T8 reaches 0, the time-out status bit (CTR0, bit 5) is set, and an interrupt can be generated if enabled (CTR0, bit 1). T8 then continues counting from FFh(see Figure 32 on page 106). 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 106 T8 (8-bit) Count Capture No T8_Enable (Set by User) Yes No Edge Present? Yes Pos What Kind of Edge? Neg T8LO8 T8HI8 %FF T8 Figure 32. DEMODULATION Mode Count Capture Flowchart When bit 4 of CTR3 is enabled, the flow of the demodulation sequence is altered. The third edge makes T8 active, and the fourth and fifth edges are captured. The capture interrupt is activated after the fifth event occurs. This mode is useful for capturing the carrier duty cycle as well as the frequency at which the first cycle is corrupted. See Figure 33 and Figure 34. 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 107 T8 (8-Bit) DEMODULATION Mode No T8_Enable CTR0, D7? Yes %FF TC8 No First Edge Present? Yes Disable T8 Enable TC8 T8_Enable Bit Set? No Yes No Edge Present? Yes T8 Time Out? Set Edge Present Status Bit and Trigger Data Capture Int. if Enabled No Yes Set Time-Out Status Bit and Trigger Time Out Int. if Enabled Continue Counting Figure 33. DEMODULATION Mode Flowchart 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 108 T8 (8-Bit) DEMODULATION Mode No T8_Enable CTR0 bit 7 Yes FFh TC8 No Third Edge Present Yes Disable T8 Enable TC8 T8_Enable Bit Set No Yes Fourth Edge Present Yes No Fifth Edge Present Yes Set Edge Present Status Capture interrupt if enabled Set Edge Present Status Bit and Trigger Data No T8 Time Out Yes Set Time-Out Status Bit and Trigger Time Out Interrupt if enabled Continue Counting Figure 34. DEMODULATION Mode Flowchart with Bit 4 of CTR3 Set 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 109 T16 TRANSMIT Mode In NORMAL or PING-PONG mode, the output of T16 when not enabled depends on CTR1, bit 0. If this bit is set to 0, T16_OUT is a 1; if set to 1, T16_OUT is 0. You can force the output of T16 to either 0 or 1 whether it is enabled or not by programming CTR1 bits [3:2] to a 10 or 11. When bit 4 of CTR3 is set, the T16 output does not update. However, time-out interrupts (flags) are still updated. In addition, the T8 carrier is not disrupted by timing out of the T16 timer. When T16 is enabled, a value of (TC16H * 256) + TC16L is loaded, and T16_OUT is switched to its initial value (CTR1, bit 0). When T16 counts down to 0, T16_OUT is toggled (in NORMAL or PING-PONG mode), an interrupt (CTR2, bit 1) is generated (if enabled), and a status bit (CTR2, bit 5) is set. See Figure 35. Z8 LXMC Data Bus CTR2 data bit 2 Positive Edge Negative Edge HI16 LO16 IRQ3 CTR2 data bits [4:3] Clock Select Clock 16-Bit Counter T16 (TC16) CTR2 data bit 1 SCLK T16_OUT TC16 Z8 LXMC Data Bus TC16 Figure 35. 16-Bit Counter/Timer Circuits Note: Global interrupts override this function as described in the Interrupts on page 127. If T16 is in SINGLE-PASS mode, it is stopped at this point (see Figure 36 on page 110). If it is in MODULO-N mode, it is loaded with TC16H * 256 + TC16L, and the counting continues (see Figure 37 on page 110). You can modify the values in TC16H and TC16L at any time. The new values take effect when they are loaded. 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 110 Caution: Do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. An initial count of 1 is not allowed. An initial count of 0 causes T16 to count from 0 to FFFEh. Transition from 0 to FFFFh is not a time-out condition. TC16H * 256 + TC16L Counts Counter Enable command; T16_OUT, switches to its initial value (CTR1 data bit 0) T16_OUT toggles, Time-out interrupt Figure 36. T16_OUT in SINGLE-PASS Mode TC16H * 256 + TC16L TC16H * 256 + TC16L TC16H * 256 + TC16L T16_OUT Counter Enable command; T16_OUT, switches to its initial value (CTR1 data bit 0) T16_OUT toggles, Time-out interrupt T16_OUT toggles, Time-out interrupt Figure 37. T16_OUT in MODULO-N Mode T16 DEMODULATION Mode You must program TC16L and TC16H to FFh. After T16 is enabled, and the first edge (rising, falling, or both depending on CTR1 bits [5:4]) is detected, T16 captures HI16 and LO16, reloads, and begins counting. 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 111 If Bit 6 of CTR2 Is 0--When a subsequent edge (rising, falling, or both depending on CTR1 bits [5:4]) is detected during counting, the current count in T16 is complemented and loaded into HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1, bit 1; bit 0) is set, and an interrupt is generated if enabled (CTR2, Bit 2). T16 is loaded with FFFFh and starts again. This T16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks). If Bit 6 of CTR2 Is 1--T16 ignores the subsequent edges in the input signal and continues counting down. A time-out of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, Bit 2). In this case, T16 does not reload and continues counting. If CTR2 bit 6 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the next edge (rising, falling, or both depending on CTR1 bits [5:4]), continuing to ignore subsequent edges. This T16 mode generally measures mark time, the length of an active carrier signal burst. If T16 reaches 0, T16 continues counting from FFFFh. Meanwhile, a status bit (CTR2 bit 5) is set, and an interrupt time-out can be generated, if enabled (CTR2 bit 1). PING-PONG Mode PING-PONG mode is only valid in TRANSMIT mode. T8 and T16 must be programmed in SINGLE-PASS mode (CTR0, bit 6; CTR2, bit 6), and PING-PONG mode must be programmed in CTR1 bits [3:2]. You can begin the operation by enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1, bit 1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT then switches to its initial value (CTR1, bit 0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops, T8 is enabled again, repeating the entire cycle. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0, bit 1; CTR2, bit 1). To stop the PING-PONG operation, write 00 to bits CTR1 bits [3:2]. See Figure 38 on page 112. Note: Enabling PING-PONG operation while the counter/timers are running may cause intermittent counter/timer function. Disable the counter/timers and reset the status flags before instituting this operation. 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 112 Enable TC8 Time-out Enable Ping-Pong CTR1 data bits [3:2] TC16 Time-out Figure 38. PING-PONG Mode Diagram Initiating PING-PONG Mode First, ensure that both counter/timers are not running. Follow the steps below to initiate the PING-PONG mode: 1. Set T8 into SINGLE-PASS mode (CTR0, bit 6) 2. Set T16 into SINGLE-PASS mode (CTR2, bit 6) 3. Set the PING-PONG mode (CTR1 bits [3:2]) These instructions are not consecutive and can occur in random order. 4. Finally, start PING-PONG mode by enabling either T8 (CTR0, D7) or T16 (CTR2, D7). The initial value of T8 or T16 must not be 1. If you stop the timer and restart the timer, reload the initial value to avoid an unknown previous value. During PING-PONG Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by hardware. The time-out bits (CTR0, bit 5; CTR2, bit 5) are set every time the counter/ timers reach the terminal count. Timer Output The output logic for the timers is displayed in Figure 39 on page 113. P34 is used to output T8_OUT when bit 0 of CTR0 is set. P35 is used to output the value of T16_OUT when bit 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 113 0 of CTR2 is set. When bit 6 of CTR1 is set, P36 outputs the logic combination of T8_OUT and T16_OUT via bits [4:5] of CTR1. P34_INTERNAL MUX P34 CTR0 data bit 0 T8_OUT AND/OR/NOR/NAND Logic T16_OUT CTR1 data bit 2 P36_INTERNAL MUX P36 MUX CTR1 data bit 3 CTR1 data bits [5:4] P35_INTERNAL CTR1 data bit 6 MUX P35 CTR2 data bit 0 Figure 39. Timer Output Circuit 19-4572; Rev 0; 4/09 Counter/Timer Functional Blocks ZLF645 Series Flash MCUs Product Specification 114 Counter/Timer Registers The following sections describe each of the Timer/Counter registers in detail. Timer 8 Capture High Register The Timer 8 Capture High register (see Table 48) holds the captured data from the output of the 8-bit Counter/Timer 0. This register contains the number of counts when the input signal is 1. Note: This register is not reset after a Stop Mode Recovery. Table 48. Timer 8 Capture High Register (HI8) Bit Field Reset R/W Address Bit Position Value Description 7 6 5 4 3 2 1 0 T8_Capture_HI 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bank D: 0Bh; Linear: D0Bh [7:0] 0hh-FFh T8_Capture_HI--Reads return captured data. Writes have no effect. Timer 8 Capture Low Register The Timer 8 Capture Low register (see Table 49 on page 115) holds the captured data from the output of the 8-bit Counter/Timer 0. Typically, this register contains the number of counts when the input signal is 0. Note: This register is not reset after a Stop Mode Recovery. 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 115 Table 49. Timer 8 Capture Low Register (LO8) Bit Field Reset R/W Address Bit Position 7 6 5 4 3 2 1 0 T8_Capture_LO 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bank D: 0Ah; Linear: D0Ah Value Description [7:0] 0hh-FFh T8_Capture_LO--Read returns captured data. Writes have no effect. Timer 16 Capture High Register The Timer 16 Capture High register (see Table 50) holds the captured data from the output of the 16-bit Counter/Timer 16. This register contains the most significant byte (MSB) of the data. Note: This register is not reset after a Stop Mode Recovery. Table 50. Timer 16 Capture High Register (HI16) Bit Field Reset R/W Address Bit Position Value Description 7 6 5 4 3 2 1 0 T16_Capture_HI 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bank D: 09h; Linear: D09h [7:0] 0hh-FFh T16_Capture_HI--Read returns captured data. Writes have no effect. 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 116 Timer 16 Capture Low Register The Timer 16 Capture Low register (see Table 51) holds the captured data from the output of the 16-bit Counter/Timer 16. This register contains the least significant byte (LSB) of the data. Note: This register is not reset after a Stop Mode Recovery. Table 51. Timer 16 Capture Low Register (LO16) Bit Field Reset R/W Address Bit Position Value Description 7 6 5 4 3 2 1 0 T16_Capture_LO 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bank D: 08h; Linear: D08h [7:0] 0hh-FFh T16_Capture_LO--Read returns captured data. Writes have no effect. Counter/Timer 16 High Hold Register The Counter/Timer 16 High Hold register (see Table 52) contains the high byte of the value loaded into the T16 timer. Note: This register is not reset after a Stop Mode Recovery. Table 52. Counter/Timer 16 High Hold Register (TC16H) Bit Field Reset R/W Address Bit Position Value Description 7 6 5 4 3 2 1 0 T16_Data_HI 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bank D: 07h; Linear: D07h [7:0] 0hh-FFh T16_Data_HI--Read/Write Data. 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 117 Counter/Timer 16 Low Hold Register The Counter/Timer 16 Low Hold register (see Table 53) contains the low byte of the value loaded into the T16 timer. Note: This register is not reset after a Stop Mode Recovery. Table 53. Counter/Timer 16 Low Hold Register (TC16L) Bit Field Reset R/W Address Bit Position Value Description 7 6 5 4 3 2 1 0 T16_Data_LO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bank D: 06h; Linear: D06h [7:0] 0hh-FFh T16_Data_LO--Read/Write Data. Counter/Timer 8 High Hold Register The Counter/Timer 8 High Hold register (see Table 54) contains the value to be counted while the T8 output is 1. Note: This register is not reset after a Stop Mode Recovery. Table 54. Counter/Timer 8 High Hold Register (TC8H) Bit Field Reset R/W Address Bit Position Value Description T8_Level_HI--Read/Write Data. 7 6 5 4 3 2 1 0 T8_Level_HI 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bank D: 05h; Linear: D05h [7:0] 0hh-FFh 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 118 Counter/Timer 8 Low Hold Register The Counter/Timer 8 Low Hold register (see Table 55) contains the value to be counted while the T8 output is 0. Note: This register is not reset after a Stop Mode Recovery. Table 55. Counter/Timer 8 Low Hold Register (TC8L) Bit Field Reset R/W Address Bit Position 7 6 5 4 3 2 1 0 T8_Level_LO 0 R/W Value 0 R/W Description 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bank D: 04h; Linear: D04h [7:0] 0hh-FFh T8_Level_LO--Read/Write Data. 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 119 Counter/Timer 8 Control Register The Counter/Timer 8 Control register (see Table 56) controls the timer function of the T8 timer. Caution: Writing 1 to CTR0[5] is the only way to reset the Terminal Count status condition. Reset this bit before using/enabling the counter/timers. Note: You must be careful when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (DEMODULATION Mode). These instructions use a Read-ModifyWrite sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers. Example: When the status of bit 5 is 1, a timer reset condition occurs. Table 56. Counter/Timer 8 Control Register (CTR0) Bit 7 T8_Enable 6 SINGLEPASS/ MODULO-N 5 Time_Out 4 3 2 1 0 T8 _Clock Capture_INT_Mask Counter_INT_Mask P34_Out Field Reset R/W Address 0 R/W 0 R/W 0 R/W 0 0 0 R/W 0 R/W 0 R/W R/W R/W Bank D: 00h; Linear: D00h 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 120 Bit Position Value Description T8_Enable--Disable/enable the T8 counter. (Note: This register bit duplicates the function of register bit 6 of the CTR3 register). [7] 0 1 [6] 0 1 [5] Read 0 1 Write 0 1 Disables the T8 counter if bit 6 of the CTR3 register is also 0. Enables the T8 counter if bit 6 of the CTR3 register is also 0 and has no effect if the T8 counter is already enabled by bit 6 of the CTR3 register being 1. SINGLE-PASS/MODULO-N MODULO-N mode. Counter reloads the initial value when terminal count is reached. SINGLE-PASS mode. Counter stops when the terminal count is reached. Time_Out--This bit is set when the T8 terminal count is reached. No counter time-out occurred. Counter time-out occurred. No effect. Reset flag to 0. Software must reset this flag before using counter/timers. T8 _Clock--Select the T8 input clock frequency.These bits are not reset upon Stop Mode Recovery. [4:3] 00 01 10 11 [2] SCLK SCLK / 2 SCLK / 4 SCLK / 8 Capture_INT_Mask--Disable/enable interrupt when data is captured into either LO8 or HI8 on a positive or negative edge detection in DEMODULATION mode. This bit is not reset upon Stop Mode Recovery. 0 1 [1] 0 1 [0] 0 1 Disable data capture interrupt. Enable data capture interrupt. Counter_INT_Mask--Disable/enable T8 time-out interrupt. This bit is not reset upon Stop Mode Recovery. Disable time-out interrupt. Enable time-out interrupt. P34_Out--Select normal I/O or T8 output function for Port 3, pin 4. P34 as port output. T8 output on P34. 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 121 T8 and T16 Common Functions Register The T8 and T16 Common Functions register (CTR1) controls the functions in common with Timer 8 and Timer 16. Table 57 describes the bits for this register. Note: Be careful to differentiate TRANSMIT mode from DEMODULATION mode, as set by CTR1[7]. The functions of CTR1[6:0] and CTR2[6] are different depending on which mode is selected. Do not change from one mode to another without first disabling the counter/timers. Table 57. Timer 8 and Timer 16 Common Functions Register (CTR1) Bit 7 Mode 6 P36 Out/ Demodulator Input 5 4 3 2 1 Initial Timer 8 Out/ Rising Edge 0 Initial Timer 16 Out/ Falling Edge Field Reset R/W Address Bit Position T8/T16 Logic/ Edge Detect Transmit Submode/ Glitch Filter 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bank D: 01h; Linear: D01h Value Description Mode--Selects the timer mode for signal transmission or demodulation. [7:0] 0 1 [6] 0 1 TRANSMIT mode. DEMODULATION mode. TRANSMIT Mode P36 Out--Select normal I/O or timer output on Port 3, Pin 6. P36 acts as normal I/O port output. P36 acts as combined Timer 8/Timer 16 output. DEMODULATION Mode Demodulator Input--Select Port 2, Pin 0 or Port 3, Pin 1 as the counter/timer input. 0 1 P31 acts as the demodulator input. If IMR[2] = 1, a P31 event can also generate an IRQ1 interrupt. To prevent this, clear IMR[2] or select P20 as input instead. P20 acts as the demodulator input. 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 122 Bit Position Value Description TRANSMIT Mode T8/T16 Logic--Defines how the Timer 8/Timer 16 outputs are combined logically. These bits are not reset upon Stop Mode Recovery. [5:4] 00 01 10 11 Output is T8 AND T16. Output is T8 OR T16. Output is T8 NOR T16. Output is T8 NAND T16. DEMODULATION Mode Edge Detect--Define the behavior of the edge detector. 00 01 10 11 [3:2] Falling edge detection. Rising edge detection. Falling and rising edge detection. Reserved. TRANSMIT Mode Submode Selection--Select NORMAL or PING-PONG mode operation, or force T16 output. When these bits are written to 00b (NORMAL mode) or 01b (PING-PONG mode), T16_OUT assumes the opposite state of bit CTR1[0] until the timer begins counting. 00 01 10 11 Normal operation. Writing 00 terminates PING-PONG mode, if it is active. PING-PONG mode. Force T16_OUT = 0 Force T16_OUT = 1 DEMODULATION Mode Glitch Filter--Define the maximum glitch width to be rejected by the counter/timer. 00 01 10 11 No filter. 4 SCLK cycle filter. 8 SCLK cycle filter. Reserved. 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 123 Bit Position Value Description TRANSMIT Mode Initial Timer 8 Out--Select the initial T8_OUT state when Timer 8 is enabled. While the timer is disabled, the opposite state is asserted on the pin to ensure that a transition occurs when the timer is enabled. Changing this bit while the counter is enabled can cause unpredictable output on T8_OUT. [1] 0 1 T8_OUT transitions from High to Low when Timer 8 is enabled. T8_OUT transitions from Low to High when Timer 8 is enabled. DEMODULATION Mode Rising Edge--Indicates whether a rising edge was detected on the input signal. Write 1 to this flag to reset it. Read 0 1 Write 0 1 [0] No rising edge detection. Rising edge detection. No effect. Reset flag to 0. TRANSMIT Mode Initial Timer 16 Out--In NORMAL or PING-PONG mode, this bit selects the initial T16_OUT state when Timer 16 is enabled. While the timer is disabled, the opposite state is asserted on the pin to ensure that a transition occurs when the timer is enabled. Changing this bit while the counter is enabled can cause unpredictable output on T16_OUT. 0 1 If CTR1[3]=0, T16_OUT transitions from High to Low when Timer 16 is enabled. If CTR1[3]=0, T16_OUT transitions from Low to High when Timer 16 is enabled. DEMODULATION Mode Falling Edge--Indicates whether a falling edge was detected on the input signal. Write 1 to this flag to reset it. Read 0 1 Write 0 1 No falling edge detection. Falling edge detection. No effect. Reset flag to 0. 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 124 Counter/Timer 16 Control Register Table 58 describes the bits for the Counter/Timer 16 Control register (CTR2). Table 58. Counter/Timer 16 Control Register (CTR2) Bit Field Reset R/W Address Bit Position Value Description T16_Enable--Disable/enable the T16 counter. (Note: This register bit duplicates the function of register bit 7 of the CTR3 register). 7 6 5 4 3 2 1 0 T16_Enable 0 R/W Single/ Time_Out Modulo-N 0 R/W 0 R/W T16 _Clock 0 R/W 0 R/W Capture_INT Counter_INT _Mask _Mask 0 R/W 0 R/W P35_Out 0 R/W Bank D: 02h; Linear: D02h [7] 0 1 Disables the T16 counter if bit 7 of the CTR3 register is also 0. Enables the T16 counter if bit 7 of the CTR3 register is also 0 and has no effect if the T16 counter is already enabled by bit 7of the CTR3 register being 1. TRANSMIT Mode (CTR1[7]=0) [6] 0 1 Single/Modulo-N--Selects Timer 16 terminal count action. MODULO-N mode. T16 reloads the initial value when terminal count is reached. SINGLE-PASS mode. T16 stops when the terminal count is reached. DEMODULATION Mode (CTR1[7]=1) Enable single-edge capture. See T16 DEMODULATION Mode on page 110. 0 1 [5] Read 0 1 Write 0 1 Timer 16 captures and reloads on all edges. Timer 16 captures and reloads on first edge only. Time_Out--This bit is set when the T16 terminal count is reached. Time_Out--This bit is set when the T16 terminal count is reached. No counter time-out occurs. Counter time-out occurred. No effect. Reset flag to 0. Software must reset this flag before using counter/timers. 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 125 Bit Position Value Description T16 _Clock--Select T16 input clock frequency. These bits are not reset upon Stop Mode Recovery. [4:3] 00 01 10 11 [2] SCLK SCLK / 2 SCLK / 4 SCLK / 8 Capture_INT_Mask--Disable/enable interrupt when data is captured into either LO16 or HI16 upon a positive or negative edge detection in DEMODULATION mode. This bit is not reset upon Stop Mode Recovery. 0 1 [1] 0 1 [0] 0 1 Disable data capture interrupt. Enable data capture interrupt. Counter_INT_Mask--Disable/enable T16 time-out interrupt. Disable T16 time-out interrupt. Enable T16 time-out interrupt. P35_Out--Select normal I/O or T8 output function for Port 3, Pin 5. P35 as port output. P35 is T16 output. Timer 8/Timer 16 Control Register The Timer 8/Timer 16 Counter/Timer register allows the start time of the T8 and T16 counters to be synchronized by simultaneously programming bits 7 and 6 to `1'. It also can freeze the T16 output value and change T8 DEMODULATION mode to capture one cycle of a carrier. Table 59 briefly describes the bits for this Bank D register. 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 126 Table 59. Timer 8/Timer 16 Control Register (CTR3) Bit Field Reset R/W Address Bit Position Value Description T16_Enable--Disable/enable the T16 counter. (Note: This register bit duplicates the function of register bit 7 of the CTR2 register). 7 6 5 4 3 2 1 0 T16_Enable 0 R/W T8_Enable 0 R/W Sync_Mode 0 R/W T16_Out Disable 0 R/W T8 Demodulate 0 R/W X -- Reserved X -- X -- Bank D: 03h; Linear: D03h [7] 0 1 [6] 0 1 [5] Disables the T16 counter if bit 7 of the CTR2 register is also 0. Enables the T16 counter if bit 7 of the CTR2 register is also 0 and has no effect if the T16 counter is already enabled by bit 7of the CTR2 register being 1. T8_Enable--Disable/enable the T8 counter. (Note: This register bit duplicates the function of register bit 7of the CTR0 register). Disables the T8 counter if bit 7of the CTR0 register is also 0. Enables the T8 counter if bit 7of the CTR0 register is also 0 and has no effect if the T8 counter is already enabled by bit 7of the CTR0 register being 1. Sync_Mode--When enabled, the first pulse of Timer 8 (the carrier) is always synchronized with Timer 16 (the demodulated signal). It can always provide a full carrier pulse. This bit is not reset upon Stop Mode Recovery. 0 1 [4] Disable SYNC mode. Enable SYNC mode. T16_Out Disable--Set this bit to disable toggling of the Timer 16 output. Timeout interrupts are still generated. This bit is not reset upon Stop Mode Recovery. 0 1 [3] T16 toggles normally. T16 toggle is disabled. T8 Demodulate--(Capture one cycle) This bit is not reset upon Stop Mode Recovery. 0 1 T8 captures events normally. T8 becomes active on the third edge, captures events on the fourth and fifth edges, and generates an interrupt on the fifth edge. After a T8 time-out the event count resets to 0 and the fourth and fifth edges are captured again. Reserved--Always reads 111b. Must be written to 1. [2:0] -- 19-4572; Rev 0; 4/09 Counter/Timer Registers ZLF645 Series Flash MCUs Product Specification 127 Interrupts The ZLF645 MCU features six interrupts (see Table 61 on page 129). These interrupts are maskable and prioritized (see Figure 40 on page 128). The six interrupt sources are divided as follows: * * * Three sources are claimed by Port 3 lines P33:P31 Two by the counter/timers (see Table 61) One for low-voltage detection P32 and UART receiver share the same interrupt. Only one interrupt can be selected as a source. When the UART receiver is enabled, P32 is no longer used as an interrupt source. The UART transmit interrupt and UART baud rate interrupt use the same interrupt as the P33 interrupt. The user selects which source triggers the interrupt. When bit 7 of UCTL is 1, the UART transmit interrupt is the source. When bit 7 of UCTL is 0 and bit 5 of UCTL is 1, the BRG interrupt is selected. The Interrupt Mask Register (globally or individually) enables or disables the six interrupt requests. The source for IRQ1 is determined by bit 1 of the Port 3 Mode register (P3M) and bit 4 of the SMR4 register. If P3M[1]=0 (DIGITAL mode) and SMR4[4]=0, pin P33 is the IRQ1 source. If P3M[1]=1 (ANALOG mode) or SMR4[4]=1 (SMR interrupt enabled), the output of the Stop Mode Recovery source logic is used as the source for the interrupt. For more details, see Stop Mode Recovery Interrupt on page 144. Table 60. Interrupt Control Registers Address (Hex) 12-Bit Bank 8-Bit Register Description Mnemonic Reset XXh 00h 0XXX_XXXXb Page No 0F9 0FA 0FB All All All F9 FA FB Interrupt Priority Register Interrupt Request Register Interrupt Mask Register IPR IRQ IMR 130 131 133 19-4572; Rev 0; 4/09 Interrupts ZLF645 Series Flash MCUs Product Specification 128 P32 UART R X P33 Stop Mode Recovery Source UCTL bits 5 & 6 = 11 0 1 0 1 P3M[1] OR SMR4[4] UART BRG Interrupt 0 1 UCTL bits 7, 6, and 0 = 001 UART T X P31 0 1 UCTL bits 5 and 7 = 11 IRQ Register (bits 6 & 7) IRQ2 Interrupt Edge Select IRQ0 IRQ1 Timer 16 IRQ3 Timer 8 IRQ4 Low-Voltage Detection IRQ5 Interrupt Request Interrupt Mask Register 5 Interrupt Priority Register Global Interrupt Enable Interrupt Request Priority Logic Vector Select Figure 40. Interrupt Block Diagram 19-4572; Rev 0; 4/09 Interrupts ZLF645 Series Flash MCUs Product Specification 129 Table 61. Interrupt Types, Sources, and Vectors Vector Location (Program Memory) Name Source Comments IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 P32, UART Rx P33, UART Tx, BRG, SMR Event P31 Timer 16 Timer 8 Low-Voltage Detection 0,1 2, 3 4, 5 6, 7 8, 9 10, 11 External (P32), Rising, Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising, Falling Edge Triggered Internal Internal Internal When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle activates when an interrupt request is granted. As a result, all subsequent interrupts are disabled, and the Program Counter and Status Flags are saved. The cycle then branches to the Program Memory vector location reserved for that interrupt. All ZLF645 MCU interrupts are vectored through locations in the Program Memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked, and the Interrupt Request Register is polled to determine which of the interrupt requests require service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge triggered. These interrupts are user-programmable. The software can poll to identify the state of the pin. 19-4572; Rev 0; 4/09 Interrupts ZLF645 Series Flash MCUs Product Specification 130 Programming bits for the Interrupt Edge Select are located in the IRQ register (R250), bit 6 and bit 7. Table 62 provides the configuration. Table 62. Interrupt Request Register IRQ Bit 7 6 Interrupt Edge IRQ2 (P31) IRQ0 (P32) 0 0 1 1 0 1 0 1 F F R R/F F R F R/F Note: F = Falling Edge; R = Rising Edge. Interrupt Priority Register The Interrupt Priority register (see Table 63) defines which interrupt holds the highest priority. Interrupts are divided into three groups of two--Group A, Group B, and Group C. IPR bits 4, 3, and 0 determine which interrupt group has priority. For example, if interrupts IRQ5, IRQ1, and IRQ0 occur simultaneously when IPR[4:3,0]=001b, the interrupts are serviced in the following order: IRQ1, IRQ0, IRQ5. IPR bits 5, 2, and 1 determine which interrupt within each group has higher priority. Table 63. Interrupt Priority Register (IPR) Bit Field Reset R/W Address Bit Position Value Description Reserved Reads are undefined; writes must be 00b. Group A Priority (IRQ3, IRQ5) IRQ5 > IRQ3 IRQ3 > IRQ5 7 6 5 4 3 2 1 0 Reserved X -- X Group A Priority X W Group Priority [2:1] X W X Group B Priority X W Group C Priority X W Group Priority [0] X W Bank Independent: F9h; Linear: 0F9h [7:6] [5] -- 0 1 19-4572; Rev 0; 4/09 Interrupt Priority Register ZLF645 Series Flash MCUs Product Specification 131 Bit Position Value Description Group Priority Reserved C>A>B A>B>C A>C>B B>C>A C>B>A B>A>C Reserved Group B Priority (IRQ0, IRQ2) IRQ2 > IRQ0 IRQ0 > IRQ2 Group C Priority (IRQ1, IRQ4) IRQ1 > IRQ4 IRQ4 > IRQ1 {[4:3], [0]} 000 001 010 011 100 101 110 111 0 1 0 1 [2] [1] Interrupt Request Register Bit 7 and Bit 6 of the Interrupt Request register (see Table 64) are used to configure the edge detection of the interrupts for Port 3, bit 1 and Port 3, bit 2. The remaining bits (5 through 0) indicate the status of the interrupt. When an interrupt is serviced, the hardware automatically clears the bit to 0. Writing 1 to any of these bits generates an interrupt if the appropriate bits in the Interrupt Mask register are enabled. Writing 0 to these bits clears the interrupts. Table 64. Interrupt Request Register (IRQ) Bit Field Reset R/W Address Bit Position Value Description Interrupt Edge P31P32 P31P32 P31P32 P31P32 7 6 5 4 3 2 1 0 Interrupt Edge 0 R/W 0 R/W IRQ5 0 R/W IRQ4 0 R/W IRQ3 0 R/W IRQ2 0 R/W IRQ1 0 R/W IRQ0 0 R/W Bank Independent: FAh; Linear: 0FAh [7:6] 00 01 10 11 19-4572; Rev 0; 4/09 Interrupt Request Register ZLF645 Series Flash MCUs Product Specification 132 Bit Position Value Description IRQ5 (Low-Voltage Detection) Interrupt did not occur. Interrupt occurred. [5] Read 0 1 Write 0 1 Read 0 1 Write 0 1 Read 0 1 Write 0 1 Read 0 1 Write 0 1 Read 0 1 Write 0 1 Read 0 1 Write 0 1 Clear interrupt. Set interrupt. IRQ4 (T8 Counter) Interrupt did not occur. Interrupt occurred. [4] Clear interrupt. Set interrupt. IRQ3 (T16 Counter) Interrupt did not occur. Interrupt occurred. [3] Clear interrupt. Set interrupt. IRQ2 (Port 3 Bit 1 Input) Interrupt did not occur. Interrupt occurred. [2] Clear interrupt. Set interrupt. IRQ1 (Port 3 Bit 3 Input/SMR Event/UART TX/UART BRG) Interrupt did not occur. Interrupt occurred. [1] Clear interrupt. Set interrupt. IRQ0 (Port 3 Bit 2 Input/UART RX) Interrupt did not occur. Interrupt occurred. [0] Clear interrupt. Set interrupt. Note: The IRQ register is protected from change until an EI instruction is executed once. 19-4572; Rev 0; 4/09 Interrupt Request Register ZLF645 Series Flash MCUs Product Specification 133 Interrupt Mask Register Bits [5:0] are used to enable the interrupt. Bit 7 is the status of the master interrupt. When reset, all interrupts are disabled. When writing 1 to bit 7, you must also execute the EI instruction to enable interrupts (see Table 65). Table 65. Interrupt Mask Register (IMR) Bit Field Reset R/W Address Bit Position Value Description Master Interrupt Enable Use only DI and EI instructions to alter this bit. Always disable interrupts (DI instruction) before writing this register. All interrupts are disabled. Interrupts are enabled/disabled individually in bits [5:0]. 7 6 5 4 3 2 1 0 Master Interrupt Reserved Enable 0 R/W X -- IRQ5 Enable X R/W IRQ4 Enable X R/W IRQ3 Enable X R/W IRQ2 Enable X R/W IRQ1 Enable X R/W IRQ0 Enable X R/W Bank Independent: FBh; Linear: 0FBh [7] 0 1 [6] [5] [4] [3] [2] [1] [0] 0 0 1 0 1 0 1 0 1 0 1 0 1 Reserved Reads are undefined; Must be written to 1. Disables IRQ5. Enables IRQ5. Disables IRQ4. Enables IRQ4. Disables IRQ3. Enables IRQ3. Disables IRQ2. Enables IRQ2. Disables IRQ1. Enables IRQ1. Disables IRQ0. Enables IRQ0. 19-4572; Rev 0; 4/09 Interrupt Mask Register ZLF645 Series Flash MCUs Product Specification 134 Clock ZLF645 MCUs on-chip oscillator has a high-gain, parallel-resonant amplifier for connecting to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). Crystal Specification The crystal must be AT cut, 1 MHz to 8 MHz (maximum), with a series resistance (RS) less than or equal to 100 . The on-chip oscillator can be driven with a suitable external clock source. The crystal must be connected across XTAL1 and XTAL2 pins using the recommended capacitors from each pin to ground. The typical capacitor value is 10 pF for 8 MHz. Check with the crystal supplier for the optimum capacitance. XTAL1 C1 XTAL1 XTAL1 XTAL2 C2 XTAL2 XTAL2 Ceramic Resonator or Crystal C1, C2 = 10 pF * f = 8 MHz External Clock Ceramic Resonator f = 8 MHz *Note: preliminary value, including pin parasitics. Figure 41. Oscillator Configuration Maxim's IR MCU supports crystal, resonator, and oscillator. Most resonators have a frequency tolerance of less than 0.5%, which is enough for a remote control application. Resonator has a very fast startup time, which is around few hundred microseconds. Most crystals have a frequency tolerance of less than 50 ppm (0.005%). However, crystal needs longer startup time than the resonator. The large loading capacitance slows down the oscillation startup time. Clock oscillation must be stable before the CPU begins instruction execution. If oscillation is not present or not stable before the chip completes timeout of its Power-On Reset (POR) period, the chip's behavior could be indeterminate. 19-4572; Rev 0; 4/09 Clock ZLF645 Series Flash MCUs Product Specification 135 Maxim(R) recommends not to use more than 10 pF loading capacitor for the crystal. If the stray capacitance of the PCB or the crystal is high, the loading capacitance C1 and C2 must be reduced further to ensure stable oscillation before the TPOR (POR time is typically 5-6 ms. For more details, see Table 81 on page 169.). For Stop Mode Recovery operation, bit 5 of SMR register allows you to select the Stop Mode Recovery delay, which is the TPOR. If Stop Mode Recovery delay is not selected, the MCU executes instruction immediately after it wakes up from the STOP mode. If resonator or crystal is used as a clock source then STOP mode recovery delay needs to be selected (Bit 5 of SMR = 1). For both resonator and crystal oscillator, the oscillation ground must go directly to the ground pin of the microcontroller. The oscillation ground must use the shortest distance from the microcontroller ground pin and it must be isolated from other connections. Crystal 1 Oscillator Pin (XTAL1) The Crystal 1 Oscillator time-based input pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. Additionally, an optional external singlephase clock can be connected to the on-chip oscillator input. Crystal 2 Oscillator Pin (XTAL2) The Crystal 2 Oscillator time-based output pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator output. Internal Clock Signals (SCLK and TCLK) The CPU and internal peripherals are driven by the internal SCLK signal during normal execution. During HALT mode, the interrupt logic is driven by the internal TCLK signal. The frequency of these signals with respect to the XTAL1 clock input is selectable either by programming bit 2 of the Flash's User Option Byte 1 for no division of the XTAL1 signal input, dividing it by a factor of two, and optionally by applying an additional divide-by-16 prescaler enabled through SMR register bit 0 (see Table 69 on page 146), as displayed in Figure 42. Selecting the divide-by-16 prescaler reduces device power drawduring normal operation and HALT mode. The prescaler is disabled by a POR or Stop Mode Recovery. 19-4572; Rev 0; 4/09 Crystal 1 Oscillator Pin (XTAL1) ZLF645 Series Flash MCUs Product Specification 136 User Option Byte 1, Bit #2 0 OSC /2 /16 1 Figure 42. SCLK/TCLK Circuit SMR[0] 0 SCLK TCLK 1 19-4572; Rev 0; 4/09 Internal Clock Signals (SCLK and TCLK) ZLF645 Series Flash MCUs Product Specification 137 Reset and Power Management The ZLF645 MCU provides the following reduced-power modes, power monitoring, and reset features: * * * * * * * Note: Voltage Brownout Standby--Stops the oscillator and internal clock when the power level drops below the VBO low voltage detect point. Initiates a power-on reset when power is restored above the VBO detect point. STOP Mode--Stops the clock and oscillator, reduces the MCU supply current to a very low level until a power-on reset or Stop Mode Recovery occurs. HALT Mode--Stops the internal clock to the CPU until an enabled interrupt request is received. Voltage Detection--Optionally sets a flag if a low- or high-voltage condition occurs. The low-voltage detection flag can generate an interrupt request, if enabled. Power-On Reset--Starts the oscillator and internal clock, and initializes the system to its power-on reset defaults. Watchdog Timer--Optionally generates a Power-On Reset if the program fails to execute the WDT instruction within a specified time interval. Stop Mode Recovery--Restarts the oscillator and internal clock, and initializes most of the system to its power-on reset defaults. Some register values are not reset by a Stop Mode Recovery. For supply current values under various conditions, see DC Characteristics on page 165. Figure 43 on page 138 displays the Power-On Reset sources. Table 66 lists control registers for reset and power management features. Some features are affected by registers described in other chapters. Table 66. Reset and Power Management Registers Address (Hex) 12-Bit Bank 8-Bit Register Description Mnemonic Reset 1 1 1 1 _100 0 b XXX0 _000 0 b 0 0 1 0 _000 0 b 00h X0 X0 _00XXb Page No D0C F0A F0B F0C F0D D F F F F 0C 0A 0B 0C 0D Low-Voltage Detection Register Stop Mode Recovery Register 4 Stop Mode Recovery Register Stop Mode Recovery Register 1 Stop Mode Recovery Register 2 LVD SMR4 SMR SMR1 SMR2 140 156 146 150 152 19-4572; Rev 0; 4/09 Reset and Power Management ZLF645 Series Flash MCUs Product Specification 138 Table 66. Reset and Power Management Registers (Continued) Address (Hex) 12-Bit Bank 8-Bit Register Description Mnemonic Reset X0h 0 0 0 0 _110 1 b Page No F0E F0F F F 0E 0F Stop Mode Recovery Register 3 Watchdog Timer Mode Register SMR3 WDTMR 155 142 5-Clock Filter CLR2* RESET 18-Clock Reset Generator RESET XTAL Internal RESET Active High WDT TAP Select POR/WDT Internal RC Oscillator CLK 1 2 3 4 WDT/POR Counter Chain CLR1 VDD VBO + _ Low Operating Voltage Detection WDT 12 ns Glitch Filter From Stop Mode Recovery SMR[5] VDD 1 0 *CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers, respectively, on a Low-to-High input transition. Figure 43. Resets and Watchdog Timer 19-4572; Rev 0; 4/09 Reset and Power Management ZLF645 Series Flash MCUs Product Specification 139 Voltage Brownout Standby An on-chip voltage comparator circuit (VBO) checks that the VDD is at the required level for correct operation of the device in terms of Flash memory reads. A second on-chip comparator circuit (subVBO) checks that the VDD level is high enough for proper operation of the VBO circuit. If the VDD level drops below the VBO trip point, the ZLF645 will be held in a reset state as long as VDD remains below this trip point value, and the XTAL1 and XTAL2 oscillator circuitry will be disabled thereby stopping the clock input to the ZLF645 and saving power. If the VDD level continues to drop below the subVBO trip point, the ZLF645 will remain in a reset state and the VBO comparator circuit will be disabled for further power savings. When the power level returns to a value above the VBO trip point, the device performs a power-on reset and functions normally. STOP Mode STOP instruction turns OFF the internal clock and external crystal oscillation, thus reduc- ing the MCU supply current to a very low level. For STOP mode current specifications, see Table 80 on page 165. To enter STOP mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. Execute a NOP instruction (OpCode = FFh) immediately before the appropriate sleep instruction, as given below: FF 6F NOP STOP ; clear the pipeline ; enter STOP mode STOP mode is terminated only by a reset, such as WDT time-out, POR, or one of the Stop Mode Recovery events as described in Stop Mode Recovery Event Sources on page 144. This condition causes the processor to restart the application program at address 000Ch. Unlike a normal POR or WDT reset, a Stop Mode Recovery reset does not reset the contents of some registers and bits. Register bits not reset by a Stop Mode Recovery are highlighted in grey in the register tables. Register bit SMR[7] is set to 1 by a Stop Mode Recovery. HALT Mode HALT instruction turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers, UART, and interrupts (IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5) remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after HALT mode. 19-4572; Rev 0; 4/09 Voltage Brownout Standby ZLF645 Series Flash MCUs Product Specification 140 To enter HALT mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. Execute a NOP instruction (OpCode = FFh) immediately before the appropriate sleep instruction, as given below: FF 7F NOP HALT ; clear the pipeline ; enter HALT mode Power consumption during HALT mode can be reduced by first setting SMR[0]=1 to enable the divide-by-16 clock prescaler. Voltage Detection The Low-Voltage Detection register (LVD, register 0Ch at the expanded register bank 0Dh) provides an option to monitor the VDD voltage. The voltage detection is enabled when bit 0 of LVD register is set. After voltage detection is enabled, the VDD level is monitored in real time. The HVD flag (bit 2 of the LVD register) is set only if VDD is higher than VHVD. The LVD flag (bit 1 of the LVD register) is set only if VDD is lower than the VLVD. When voltage detection is enabled, the LVD flag also triggers IRQ5. The IRQ bit 5 latches the low voltage condition until it is cleared by instructions or reset. The IRQ5 interrupt is served if it is enabled in the IMR register. Otherwise, bit 5 of IRQ register is latched as a flag only. Note: Do not modify register P01M while checking a low voltage condition. Switching noise from Port 0 can trigger the LVD flag. Table 67. Low-Voltage Detection Register (LVD) Bit Field Reset R/W Address Bit Position Value Description 7 6 5 4 3 2 1 0 Reserved 1 R 1 R 1 R 1 R 1 R High-Battery Detect 0 R Low-Battery Detect 0 R Voltage Detect Enable 0 R/W Bank D: 0Ch; Linear: D0Ch [7:3] [2] -- 0 1 Reserved--Reads 11111b. Must be written to 1. HVD clear. High-voltage detected (VDD>VHVD) 19-4572; Rev 0; 4/09 Voltage Detection ZLF645 Series Flash MCUs Product Specification 141 Bit Position Value Description [1] [0] 0 1 0 1 LVD clear. Low-voltage detected (VDD When power is initially applied to the device, a timer circuit clocked by a dedicated on-board RC-oscillator provides the POR timer function. The POR timer circuit is a oneshot timer that keeps the internal reset signal asserted long enough for VDD and the oscillator circuit to stabilize before instruction execution begins. The reset timer is triggered by one the following conditions: * * * Initial power-on or recovery from a VBO/standby condition. Stop Mode Recovery (if register bit SMR[5] = 1). Watchdog Timer time-out. SMR[5] can be cleared to 0 to bypass the POR timer on a Stop Mode Recovery. This must only be done when using an external clock that does not require a startup delay. Caution: Failure of an application to provide a stable oscillating clock input to XTAL1 before the end of the ZLF645's POR period may result in an indeterminate chip behavior and must be avoided. For details on the POR timing range, see Table 81 on page 169 in the Electrical Characteristics chapter. Watchdog Timer The Watchdog Timer (WDT) is a retriggerable one-shot timer that resets the Z8 LXMC CPU if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags. The POR clock source is an internal RC-oscillator. Bits 0 and 1 of the WDT register control a tap circuit that determines the minimum time-out period. Bit 2 determines whether the WDT is active during HALT, and bit 3 determines WDT activity during STOP mode. Bits 4 through 7 are reserved (see Table 68 on page 142). This register is accessible only during the first 60 processor cycles (120 XTAL clocks) from the execution of the first instruction after power-on reset, watchdog timer Reset, or a Stop Mode Recovery (see Fast Stop Mode Recovery). After this point, the register cannot be modified by any means. The 19-4572; Rev 0; 4/09 Power-On Reset Timer ZLF645 Series Flash MCUs Product Specification 142 WDTMR register cannot be read. The register is located in Bank F of the Expanded Register Group at address location 0Fh. Note: This register is not reset after a Stop Mode Recovery. Table 68. Watchdog Timer Mode Register (WDTMR) Bit Field Reset R/W Address Bit Position Value Description Reserved--Reads are undefined; must write 0000. WDT During STOP Mode--Determines if WDT is active during STOP mode. Off. WDT active during STOP mode. WDT During HALT Mode--Determines if WDT is active during HALT mode. See Figure 43 on page 138. Off. WDT active during HALT mode. Time-Out Select--Selects the WDT time period (see Note below). 5 ms minimum 10 ms minimum 20 ms minimum 80 ms minimum 320 ms minimum 1, 280 ms minimum 5,120 ms minimum 0 0 0 0 7 6 5 4 3 2 1 0 -- Time-Out Select WDT During STOP WDT During HALT Mode Mode 1 1 Time-Out Select 0 1 W W W W W Bank F: 0Fh; Linear: F0Fh W W W [7] [3] -- 0 1 [2] 0 1 [6:4], [1:0] 000_00 000_01 000_10 000_11 001_XX 010_XX 100_XX Note: Although not explicitly shown above, if any two bits of bits 6 through 4 are programmed to 1 or if all three bits are programmed to 0, then the time-out period depends on bits 1 and 0 only as shown for the [6:4]=000 case. Using the Watchdog Timer As a Stop Mode Recovery Source As mentioned previously, timeout of the Watchdog Timer generates a chip reset that removes the ZLF645 from STOP mode. This feature is used to configure the ZLF645 to automatically exit STOP mode, once it is in STOP mode. This is done within a set maximum period of time based upon the Watchdog Timer timeout setting. In this way, the 19-4572; Rev 0; 4/09 Watchdog Timer ZLF645 Series Flash MCUs Product Specification 143 ZLF645 is configured to periodically enter and exit STOP mode until some action is necessary by the application. Follow the steps below to configure the ZLF645 for this mode of operation: 1. Provide program code that, within 60 processor clock cycles of the start of code execution after reset, programs bits 6 through bit 4 and bit 1 through 0 of the Watchdog Timer Register (WDTMR) with the time-out setting required. Also ensure bit 3 of the WDTMR register is `1', configuring the WDT for counting once enabled, even with the ZLF645 in STOP mode. 2. Execute the WDT instruction to enable counting of the Watchdog Timer. 3. Include a STOP instruction after the program code for steps 1 & 2 above, that puts the ZLF645 into STOP mode when no action is required by the ZLF645. Once the Watchdog Timer has been enabled through the WDT instruction it will begin counting and continue counting even after the ZLF645 has entered STOP mode, due to the bit 3 of the WDTMR register being `1'. Once the WDT has reached its time-out value, it will initiate a reset condition that takes the ZLF645 out of STOP mode. This reset condition will not cause the WDTMR register to be reset and it will retain its previous programming. Upon completion of the reset the WDT will enter a disabled state and stop counting. Execution of a new WDT instruction is necessary to cause the Watchdog Timer to reset to its start count state and to start counting again. It is important to note that if a time-out of the Watchdog Timer occurs with STOP mode inactive, the reset generated will cause a reset of the WDTMR register and it will not retain its previously programmed value. In either case of STOP mode being active or inactive during Watchdog Timer time-out, the WDT will go to a disabled state upon completion of reset. Reset/Stop Mode Recovery Status Read-only bit SMR[7]=0, if the previous reset was initiated by a Power-On Reset (including Voltage Brownout or WDT resets). SMR[7]=1, if the previous reset was initiated by a Stop Mode Recovery. A power-on, Voltage Brownout, or WDT reset restores all registers to their Power-On Reset defaults. A Stop Mode Recovery restores most registers to their Power-On Reset defaults. Register bits not reset by a Stop Mode Recovery are highlighted in grey in the register tables. Register bit SMR[7] is set to 1 instead of reset by a Stop Mode Recovery. Fast Stop Mode Recovery SMR[5] can be cleared to 0 before entering STOP mode to bypass the default TPOR reset timer on Stop Mode Recovery. See Voltage Brownout Standby on page 139. If SMR[5]=0, the Stop Mode Recovery source must be kept active for at least 10 input clock periods (TpC). 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 144 Note: SMR[5] must be set to 1 if using a crystal or resonator clock source. The TPOR delay allows the clock source to stabilize before executing instructions. Stop Mode Recovery Interrupt Software can set register bit SMR4[4] = 1 to enable routing of Stop Mode Recovery events to IRQ1 and to Port 3, Pin 3. In this configuration, if an IRQ1 interrupt occurs, register bit P3[3] = 0 indicates that a Stop Mode Recovery event is occurring. Stop Mode Recovery Event Sources Any Port 2 or Port 3 input pin can be configured to generate a Stop Mode Recovery event, either individually or in various logical combinations. The ZLF645 MCU provides the following registers for Stop Mode Recovery source configuration and status: * * * * * SMR Register--Selects one Port 3, Pin 1-3 pin state or one of three Port 2 pin logical combinations to generate an event when a defined 0 or 1 level occurs. SMR1 Register--Configures one or more Port 2 input pins (0-7) to latch the latest read or write value and generate an event when the pin state changes. SMR2 Register--Selects one of seven Port 2 and 3 pin logical combinations to generate an event when a defined 0 or 1 level occurs. SMR3 Register--Configures one or more Port 3 input pins (0-3) to latch the latest read or write value and generates an event when the pin state changes. SMR4 Register--Enables routing of SMR events to IRQ1. Indicates whether port data has been latched for SMR1 or SMR3 event monitoring, and whether the latch was on a port read or write. A Stop Mode Recovery event occurs if any of the sources defined in the SMR, SMR1, SMR2, and SMR3 registers are active. SMR Register Events The SMR register function is similar to the standard Stop Mode Recovery feature used in previous Z8(R) CPU-compatible parts. Register bits SMR[4:2] are set to select one of six event modes, as displayed in Figure 44 on page 145. The output of the corresponding logic is compared to the state of SMR[6]; when they are the same, a Stop Mode Recovery event is generated. If SMR[4:2]=000, no event source is selected by SMR. The state SMR[4:2]=001 is reserved and selects no event in this device. The logic configured by the SMR register ignores any port pins that are configured as output or selected as source pins in registers SMR1 or SMR3. The SMR register is summarized in Table 69 on page 146. 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 145 SMR[4:2] = 000 VCC SMR[4:2] = 010 P31 SMR[4:2] = 011 P32 This SMR register logic ignores any pin configured as an output in the P2M or P3M registers or as a source in the SMR1 or SMR3 registers. SMR[4:2] = 100 P33 SMR[4:2] = 101 P27 SMR[4:2] = 110 P20 P23 SMR[4:2] = 111 P20 P27 SMR[6] SMR P3M[1] OR SMR4[4] 0 1 To IRQ1 And P0[3] SMR1 SMR2 SMR3 To RESET and WDT Circuitry (Active Low) Figure 44. SMR Register-Controlled Event Sources 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 146 [ Table 69. Stop Mode Recovery Register (SMR) Bit Field Reset R/W Address Bit Position Value Description Stop Flag--Indicates whether last startup was power-on reset or Stop Mode Recovery. A write to this bit has no effect. Power-on reset. Stop Mode Recovery. Stop Mode Recovery Level--Selects whether an SMR[4:2]-selected SMR is initiated by a Low or High level at the XOR-gate input (see Figure 44 on page 145). Low. High. Stop Delay--Controls the reset delay after recovery. Must be 1 if using a crystal or resonator clock source. Off. On. Stop Mode Recovery Source--Specifies a Stop Mode Recovery wake-up source at the XOR gate input (see Figure 44 on page 145). This value is not changed by a Stop Mode Recovery. The following equations ignore any Port pin configured as output or selected in SMR1 or SMR3. No SMR register source selected. Reserved. P31. P32. P33. P27. Port 2 NOR 0-3. Port 2 NOR 0-7. 7 6 5 4 3 2 1 0 Stop Flag 0 R Stop Mode Recovery Level 0 W Stop Delay 1 W Stop Mode Recovery Source 0 W 0 W 0 W Reset Time Reduction 0 W SCLK/TCLK Divide-by-16 0 W Bank F: 0Bh; Linear: F0Bh [7] 0 1 [6] 0 1 [5] 0 1 [4:2] 000 001 010 011 100 101 110 111 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 147 Bit Position Value Description SMR Short Reset Time--Controls whether the devices SMR reset period is equivalent to the RC oscillator based POR reset period or whether it depends on the detection of XTAL1 clock oscillation. Unless SMR[5]=1, the SMR reset period is equivalent to the devices RC oscillator based POR reset period and falls in the range of 2.5 ms to 10 ms. Unless SMR[5]=1, the SMR reset period falls in a range of a minimum of 2.5 ms from chip power up or a maximum of 2.5 ms from when the XTAL1 clock reaches a peak-to-peak amplitude of oscillation greater than 250 mV. SCLK/TCLK Divide-by-16 Select--Controls a divide-by-16 prescaler of the internal SCLK/TCLK signal (see Internal Clock Signals (SCLK and TCLK) on page 135). A power-on reset or Stop Mode Recovery clears this bit to 0. Off. On. [1] 0 1 [0] 0 1 SMR1 Register Events The SMR1 register can be used to configure one or more Port 2 pins to be compared with a written or sampled reference value and generate a Stop Mode Recovery event when the pin state differs from the reference value. To configure a Port 2 pin as an SMR1 event source, ensure it is configured as an input in the P2M register, then set the corresponding SMR1 register bit. By default, a Stop Mode Recovery event occurs when the pin's state is zero. After a Port 2 pin is configured as an SMR1 source, any subsequent read from or write to the P2 register latches the read or write value for reference. A Stop Mode Recovery event occurs when the pin's state differs from the last reference value latched. The SMR1 source logic is displayed in Figure 45 on page 149. The program can read register bits SMR4[1:0] to determine whether the Port 2 pins trigger a Stop Mode Recovery on a change from the last read value (SMR4[1:0]=01), or on a change from the last written value (SMR4[1:0]=10). Software can clear SMR4[1:0] to 00 to restore the default behavior (configured pins trigger when their state is 0). The SMR1 register is summarized in Table 70 on page 150. 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 148 After the following example code is executed, a 1 on P20 will wake the part from STOP mode: LD P2M, #%FF SRP #%0F LD SMR1, #%01 SRP #%00 LD P2, #%00 NOP STOP ;Set Port 2 to inputs. ;Point to expanded bank F ;Select P20 for SMR1. ;Point to bank 0 ;Write 00h to Port 2, so the P20 reference ;value is 0, and a 1 on P20 wakes the part. After the following example code is executed when the value of P2 is 00h, a 1 on P20 will wake the part from STOP mode: LD P2M, #%FF SRP #%0F LD SMR1, #%01 SRP #%00 LD R6, P2 NOP STOP ;Set ports to inputs. ;Point to expanded bank F ;Select P20 for SMR1. ;Point to bank 0 ;If a 0 is read from Port 2, the P20 reference ;value is 0, so a 1 on P20 wakes the part. 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 149 Individual Port 2 Pin SMR Logic, n = 0 _ 7 Bit P2M [n] To SMR1 Bit SMR1 [n] Port 2, Pin n Bit P2[n] D Q P33 Port 2 Read/Write IRQ1 P3M[1] OR SMR4[4] P20 Logic P21 Logic P22 Logic P23 Logic P24 Logic P25 Logic P26 Logic P27 Logic SMR1 SMR SMR2 SMR3 0 1 Register P3, bit 3 To RESET and WDT Circuitry (Active Low) Figure 45. SMR1 Register-Controlled Event Sources 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 150 Table 70. Stop Mode Recovery Register 1 (SMR1) Bit Field Reset R/W Address Bit Position Value Description 7 6 5 4 3 2 1 0 P27 Stop Select 0 W P26 Stop Select 0 W P25 Stop Select 0 W P24 Stop Select 0 W P23 Stop Select 0 W P22 Stop Select 0 W P21 Stop Select 0 W P20 Stop Select 0 W Bank F: 0Ch; Linear: F0Ch [7] [6] [5] [4] [3] [2] [1] [0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P27 not selected. P27 selected as an SMR source. P26 not selected. P26 selected as an SMR source. P25 not selected. P25 selected as an SMR source. P24 not selected. P24 selected as an SMR source. P23 not selected. P23 selected as an SMR source. P22 not selected. P22 selected as an SMR source. P21 not selected. P21 selected as an SMR source. P20 not selected. P20 selected as an SMR source. Note: This register is not reset after a Stop Mode Recovery. SMR2 Register Events The SMR2 register function is similar to the standard Stop Mode Recovery feature used in previous Z8 CPU-compatible parts. Register bits SMR2[4:2] are set to select one of seven event modes, as displayed in Figure 46. The output of the corresponding logic is compared to the state of SMR2[6]; when they are the same, a Stop Mode Recovery event is generated. If SMR2[4:2]=000, no event source is selected by SMR2. 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 151 The logic configured by the SMR2 register ignores any port pins that are configured as an output, or that are selected as source pins in registers SMR1 or SMR3. The SMR2 register is summarized in Table 71 on page 152. SMR2[4:2] = 000 VCC SMR2[4:2] = 001 P20 P23 SMR2[4:2] = 010 P20 P27 SMR2[4:2] = 011 P31 P32 P33 This SMR2 register logic ignores any pin configured as an output in the P2M or P3M registers or as a source in the SMR1 or SMR3 registers. SMR2[4:2] = 100 P31 P32 P33 P33 To IRQ1 And P0[3] SMR2[4:2] = 101 P31 P32 P33 P00 P07 P31 P32 P33 P00 P07 P31 P32 P33 P20 P21 P22 P3M[1] OR SMR4[4] 0 1 SMR2[4:2] = 110 SMR SMR1 SMR2[4:2] = 111 SMR2 SMR3 To RESET and WDT Circuitry (Active Low) SMR2[6] Figure 46. SMR2 Register-Controlled Event Sources 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 152 Table 71. Stop Mode Recovery Register 2 (SMR2) Bit Field Reset R/W Address Bit Position Value Description Reserved--Read is undefined; write must be 0. Stop Mode Recovery Level 2 Selects whether an SMR2[4:2]-selected SMR is initiated by a Low or High level at the XOR-gate input (see Figure 46 on page 151). Low. High. Reserved--Read is undefined; Must be written to 1. Stop Mode Recovery Source Specifies a Stop Mode Recovery wake-up source at th e XOR gate input (see Figure 46 on page 151). Additional sources can be selected by SMR, SMR1, and SMR3 registers. If more than one source is selected, any selected source event causes a Stop Mode Recover y. The following equations ignore any Port pin that is selected in register SMR1 or configured as an output. No SMR2 register source selected. NAND of P23:P20. NAND of P27:P20. NOR of P33:P31. NAND of P33:P31. NOR of P33:P31, P00, P07. NAND of P33:P31, P00, P07. NAND of P33:P31, P22:P20. Reserved--Read is undefined; write must be 00b. 7 6 5 4 3 2 1 0 Reserved X -- Stop Mode Recovery Level 2 0 W Reserved X -- Stop Mode Recovery Source 0 W 0 W 0 W Reserved X -- X Bank F: 0Dh; Linear: F0Dh [7] [6] -- 0 1 [5] [4:2] -- 000 001 010 011 100 101 110 111 [1:0] -- Note: This register is not reset after a Stop Mode Recovery. SMR3 Register Events The SMR3 register can be used to configure one or more of Port 3, pins 0-3 to be compared to a written or sampled reference value and generate a Stop Mode Recovery event when the pin state differs from the reference value. 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 153 To configure a Port 3 input pin as an SMR3 event source set the corresponding SMR3 register bit. By default, a Stop Mode Recovery event occurs when the pin's state is zero. After a Port 3 pin is configured as an SMR3 source, any subsequent read from or write to the P2 register latches the read or written value for reference. A Stop Mode Recovery event occurs when the pin's state differs from the last reference value latched. The SMR3 source logic is displayed in Figure 47. The program can read register bits SMR4[3:2] to determine whether the Port 3 pins trigger a Stop Mode Recovery on a change from the last read value (SMR4[3:2]=01), or on a change from the last written value (SMR4[3:2]=10). Software can clear SMR4[3:2] to 00 to restore the default behavior (configured pins trigger when their state is 0). The SMR3 register is summarized in Table 69 on page 146. After the following example code is executed, a 1 on P30 will wake the part from STOP mode. LD SMR3, #%01 LD P3, #%00 NOP STOP ;Select P30 from SMR3. ;Write 00h to Port 3, so the P30 reference ;value is 0, and a 1 on P30 wakes the part. After the following example code is executed when the value of P3 is 00h, a 1 on P30 will wake the part from STOP mode. LD SMR3, #%01 LD R6, P3 NOP STOP ;Select P30 for SMR3. ;If a 0 is read from Port 3, the P30 reference ;value is 0, so a 1 on P30 wakes the part. 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 154 Individual Port 3 Pin SMR Logic, n = 0 _ 3 Bit SMR3 [n] To SMR3 Port 3, Pin n Bit P3[n] D Q P33 Port 3 Read/Write P3M[1] OR SMR4[4] P30 Logic P31 Logic P32 Logic P33 Logic SMR SMR1 SMR3 SMR2 0 1 To IRQ1 And P0[3] To RESET and WDT Circuitry (Active Low) Figure 47. SMR3 Register-Controlled Event Sources 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 155 Table 72. Stop Mode Recovery Register 3 (SMR3) Bit Field Reset R/W Address Bit Position Value Description Reserved--Reads undefined; Must be written to 1. 7 6 5 4 3 2 1 0 -- X -- X -- X -- X -- P33 MR Select 0 W P32 SMR S Select 0 W P31 SMR Select 0 W P30 SMR Select 0 W Bank F: 0Eh; Linear: F0Eh [7:4] [3] [2] [1] [0] -- 0 1 0 1 0 1 0 1 P33 not selected. P33 SMR source selected. P32 not selected. P32 SMR source selected. P31 not selected. P31 SMR source selected. P30 not selected. P30 SMR source selected. Note: This register is not reset after a Stop Mode Recovery. 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 156 Stop Mode Recovery Register 4 The Stop Mode Recovery register 4 (see Table 73) enables the SMR interrupt source and indicates the reference value status for registers SMR1 and SMR3. Table 73. Stop Mode Recovery Register 4 (SMR4) Bit Field Reset R/W Address Bit Position Value Description Reserved--Reads are undefined; must write 000b. SMR IRQ Enable If P3M[1]=0, SMR events do not generate an interrupt. SMR events generate an interrupt on IRQ1. Port 3 SMR Status No Read or Write of the P3 register occurs. P3 Read occurs; used as SMR3 reference. P3 Write occurs; used as SMR3 reference. Reserved. Port 2 SMR Status No Read or Write of the P2 register occurs. P2 Read occurs; use P2 Read as SMR1 reference. P2 Write occurs; use P2 Write as SMR1 reference. Reserved. 7 6 5 4 3 2 1 0 Reserved X -- X -- X -- SMR IRQ Enable 0 R/W Port 3 SMR Status 0 R/W 0 R/W Port 2 SMR Status 0 R/W 0 R/W Bank F: 0Ah; Linear: F0Ah [7:5] [4] -- 0 1 00 01 10 11 00 01 10 11 [3:2] [1:0] Note: This register is not reset after a Stop Mode Recovery. 19-4572; Rev 0; 4/09 Reset/Stop Mode Recovery Status ZLF645 Series Flash MCUs Product Specification 157 Z8 LXMC CPU Programming Summary The following sections provide a summary of information useful for programming the Z8 LXMC CPU included in this device. For more details on the Z8 LXMC CPU and its instruction set, refer to Z8(R) LXMC CPU Core User Manual (UM0215). Addressing Notation Table 74 summarizes Z8 LXMC CPU addressing modes and symbolic notation. The text variable n represents a decimal number; aa represents a hexadecimal address; and LABEL represents a label defined elsewhere in the assembly source. In reference notation, only lowercase is used to distinguish 4-bit addressed working registers (r1, r2) from 8-bit addressed registers (R1, R2). The numerals 1 and 2, respectively, indicate whether the register is used for destination or source addressing. . Table 74. Symbolic Notation for Operands Assembly Operand Symbol Description Condition Code cc represents a condition code mnemonic. See Condition Codes on page 161. Immediate Data IM represents an Immediate Data value, prefixed by # in assembly language where n = 0 to 255. The immediate value follows the instruction opcode in Program Memory. Working Register r1 or r2 represents the name, Rn, of a working register, where n = 0, 1, 2,..., 15. The equivalent 12-bit address is {RP[3:0], RP[7:4], n}. Working Register Pair rr1 or rr2 represents th e name, R n, of a working registe r pair, wh ere n = 0, 2, 4,..., 14. The equivalent 12-bit address is {RP[3:0], RP[7:4], n}. Register R1 or R2 represents an 8-bit register address. For addresses 00h-DFh or F0h-FFh, the equivalent 12-bit address is {RP[3:0], %aa}. For addresses E0h-EFh (escaped mode), the equivalent 12-bit address is {RP[3:0], RP[7:4], %aa[3:0]}. cc IM - #n r1 r2 rr1 rr2 R1 R2 Rn RRn %aa 19-4572; Rev 0; 4/09 Z8 LXMC CPU Programming Summary ZLF645 Series Flash MCUs Product Specification 158 Table 74. Symbolic Notation for Operands (Continued) Assembly Operand Symbol Description Register Pair (8-bit Address) RR1 or RR2 represents the 8-bit address of a register pair. For addresses 00h-DFh or F0h-FFh, the equivalent 12-bit address is {RP[3:0], %aa}. For addresses E0h-EFh (escaped mode), the equivalent 12-bit address is {RP[3:0], RP[7:4], %aa[3:0]}. Indirect Working Register Ir1 or Ir2 represents the name a working register, Rn, where n = 0, 1, 2,..., 15. @ indicates Indirect Working register addressing using an 8-bit effective address contained in the specified working register. The accessed register's equivalent 12-bit address is {RP[3:0], 8-bit effective address}. Indirect Working Register Pair Irr1 or Irr2 represents the name of a working register pair, RRn, where n = 0, 2, 4,..., 14. @ indicates Indirect Working register addressing using an effective address in the specified working register pair. Depending on th e instruction, the effective address is in the register file (12-bit address) or Program/Constant Memory (16-bit address). Indirect Register IR1 or IR2 represents the 8-bit address of a register. @ indicates Indirect register addressing using an 8-bit effective address contained in the specified r egister. The accessed register's equivalent 12-bit address is {RP[3:0], 8-bit effective address}. Indirect Register Pair IRR1 represents the 8-bit address of a register. @ indicates Indirect register addressing with a 16-bit effective address (in Program Memory) contained in the specified register pair. Indexed (X) Addressing X represents the 8-bit base address to which the offset is added. r1 or r2 represents the name, Rn, of a working r egister containing the 8-bit signed offset. The 8-bit effective address is the sum of X and the contents of working register Rn. The accessed register's equivalent 12-bit address is {RP[3:0], 8-bit effective address}. RR1 RR2 %aa Ir1 Ir2 @Rn Irr1 Irr2 @RRn IR1 IR2 @%aa IRR1 @%aa X(r1) X(r2) %aa(Rn) 19-4572; Rev 0; 4/09 Addressing Notation ZLF645 Series Flash MCUs Product Specification 159 Table 74. Symbolic Notation for Operands (Continued) Assembly Operand Symbol Description Direct Address (JP, CALL) In a JP or CALL operand, DA is a 16-bit Program Memory address in the range of 0000H to FFFFH. DA replaces the contents of the Program Counter for execution to continue at a new location in Program Memory. In assembly source, the address is represented as a label. Relative Address (JR, DJNZ) RA is a signed 8-bit Program Memory offset in the range +127 to -128, relative to the address of the n ext instruction in Program Memory. In a JR or DJNZ operation, RA is added to the pr ogram counter to cause execution to continue at a new location in Program Memory. In assembly source, the jump address is represented as an absolute label, and the assembler calculates RA. DA LABEL RA LABEL Table 75 lists additional symbols that are used throughout the instruction set summary. Table 75. Additional Symbols Symbol Definition dst src @ C SP PC FLAGS RP # b % h Destination Operand Source Operand Indirect Address Prefix Carry Flag Stack Pointer Value Program Counter Flags Register Register Pointer Immediate Operand Prefix Binary Number Suffix Hexadecimal Number Prefix Hexadecimal Number Suffix Assignment of a value. For example, dst dst + src indicates the result is stored in the destination 19-4572; Rev 0; 4/09 Addressing Notation ZLF645 Series Flash MCUs Product Specification 160 Table 75. Additional Symbols (Continued) Symbol ~ Definition Exchange of two values One's complement unary operator Flags Register The Flags register (see Table 76) informs the current status of the Z8(R) CPU. It contains six bits of status information. Table 76. Flags Register (FLAGS) Bit Field Reset R/W Address Bit Position Value Description Carry Flag (C) Set when the result of an arithmetic operation generates a carry out of or a borrow into the high-order bit (bit 7) of the result. Also used in rotate and shift instructions. Flag Clear Flag Set Zero Flag (Z) Set when the result of an arithmetic operation is 0. Flag Clear Flag Set Sign Flag (S) Stores the value of the most significant bit (msb) following an arithmetic, logical, rotate, or shift instruction. Flag Clear Flag Set Overflow Flag (O) Set when the result of an arithmetic operation is greater than 127. Flag Clear Flag Set 7 6 5 4 3 2 1 0 C X R/W Z X R/W S X R/W O X R/W D X R/W H X R/W F1 X R/W F2 X R/W Bank Independent: FCh; Linear: 0FCh [7] 0 1 [6] 0 1 [5] 0 1 [4] 0 1 19-4572; Rev 0; 4/09 Flags Register ZLF645 Series Flash MCUs Product Specification 161 Bit Position Value Description Decimal Adjust Flag (D) Used for binary-coded decimal (BCD) arithmetic. Flag Clear Flag Set Half Carry Flag (H) Set when a carry out of or borrow into bit 3 of an arithmetic operation occurs. Flag Clear Flag Set User Flag 1 (F1) Available to software for use as a general-purpose bit. Bit Clear Bit Set User Flag 2 (F2) Available to software for use as a general-purpose bit. Bit Clear Bit Set [3] 0 1 [2] 0 1 [1] 0 1 [0] 0 1 Condition Codes The C, Z, S, and V flags control the operation of the conditional jump (JP cc and JR cc) instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc). Table 77 summarizes the condition codes. Some binary condition codes can be created using more than one assembly code mnemonic. The result of the flag test operation determines if the conditional jump executes. Table 77. Condition Codes Binary Hex Assembly Mnemonic Definition Flag Test Operation 0000 0001 0010 0011 0100 0101 0110 0110 0 1 2 3 4 5 6 6 F LT LE ULE OV Ml Z EQ Always False Less than Less than or Equal Unsigned Less than or Equal Overflow Minus Zero Equal - (S XOR V) = 1 (Z OR (S XOR V)) = 1 (C OR Z) = 1 V=1 S=1 Z=1 Z=1 19-4572; Rev 0; 4/09 Condition Codes ZLF645 Series Flash MCUs Product Specification 162 Table 77. Condition Codes (Continued) Binary Hex Assembly Mnemonic Definition Flag Test Operation 0111 0111 1000 1001 1010 1011 1100 1101 1110 1110 1111 1111 7 7 8 9 A B C D E E F F C ULT T (or blank) GE GT UGT NOV PL NZ NE NC UGE Carry Unsigned Less than Always True Greater than or Equal Greater than Unsigned Greater than No Overflow Plus Non-Zero Not Equal No Carry Unsigned Greater than or Equal C=1 C=1 - (S XOR V) = 0 (Z OR (S XOR V)) = 0 (C = 0 AND Z = 0) V=0 S=0 Z=0 Z=0 C=0 C=0 19-4572; Rev 0; 4/09 Condition Codes ZLF645 Series Flash MCUs Product Specification 163 Electrical Characteristics Absolute Maximum Ratings A stress greater than listed in Table 78 may cause permanent damage to the device. Functional operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs must be tied to one of the supply voltages (VDD or VSS). Table 78. Absolute Maximum Ratings Parameter Min Max Units Ambient temperature under bias Storage temperature Voltage on any pin with respect to VSS* Voltage on VDD pin with respect to VSS Maximum current on input and/or inactive output pin Maximum output current from active output pin Maximum current into VDD or out of VSS *This voltage applies to all pins except VDD, P32, and P33. 0 -65 -0.3 -0.3 -5 -25 -- +70 +150 +4.0 +3.6 +5 +25 75 C C V V A mA mA 19-4572; Rev 0; 4/09 Electrical Characteristics ZLF645 Series Flash MCUs Product Specification 164 Standard Test Conditions The characteristics listed in this product specification apply for standard test conditions. All voltages are referenced to Ground. Positive current flows into the referenced pin (see Figure 48). From Output Under Test I 150 pF Figure 48. Test Load Diagram Capacitance Table 79 lists the capacitance. Table 79. Capacitance Parameter Maximum Input capacitance Output capacitance I/O capacitance 12 pF 12 pF 12 pF Note: TA = 25 C, Vcc = GND = 0 V, f = 1.0 MHz, unmeasured pins return to GND. This voltage applies to all pins except VDD, P32, and P33. 19-4572; Rev 0; 4/09 Standard Test Conditions ZLF645 Series Flash MCUs Product Specification 165 DC Characteristics Table 80 describes the direct current (DC) characteristics of the ZLF645 Flash MCU. Table 80. DC Characteristics TA = 0 C to +70 C Symbol Parameter VCC Min Typ Max Units Conditions VCC VCH VCL VIH VIL VOH1 VOH2 Supply Voltage1 Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output High Voltage (P36, P37, P00, and P01) Output Low Voltage Output Low Voltage (P00, P01, P36, and P37) Comparator Input Offset Voltage Comparator Reference Voltage Input Leakage Input Leakage IR Amp (P31) Output Leakage Supply Current2, 3 -- 1.9-3.6 1.9-3.6 1.9-3.6 1.9-3.6 1.9-3.6 1.9-3.6 1.9 0.8 VCC VSS-0.3 0.7 VCC VSS-0.3 VCC-0.4 VCC-0.8 -- -- -- -- -- -- -- 3.6 VCC + 0.3 0.4 VCC + 0.3 0.2 Vcc -- -- V V V V V V V See Note 5. Driven by External Clock Generator Driven by External Clock Generator -- -- IOH = -0.5 mA IOH = -7 mA VOL1 VOL2 1.9-3.6 1.9-3.6 -- -- -- -- 0.4 0.8 V V IOL = 4.0 mA IOL = 10 mA VOFFSET VREF IIL IIL1 IOL ICC 1.9-3.6 1.9-3.6 1.9-3.6 1.9-3.6 1.9-3.6 1.9 3.6 1.9 3.6 -- 0 -1 -2.5 -1 -- -- -- -- -- -- -- -- -- 1 2 2 4 25 VCC -1.75 1 -12 1 2 4 3 6 mV V -- -- VIN = 0 V, VCC; pull-ups disabled VIN = 0 V, IR amp enabled VIN = 0 V, VCC See Note 7. See Note 8. A A A mA mA mA mA 19-4572; Rev 0; 4/09 DC Characteristics ZLF645 Series Flash MCUs Product Specification 166 Table 80. DC Characteristics (Continued) TA = 0 C to +70 C Symbol Parameter VCC Min Typ Max Units Conditions ICC1 Standby Current2, 3 (HALT mode) 1.9 3.6 1.9 3.6 -- -- -- -- -- -- -- -- -- 1.8 2.3 -- -- 0.7 1.2 0.9 2 1.6 1.8 5 8 1.2 1.85 2.4 2.7 -- 1.6 2.0 2 3 8 10 20 30 6 1.9 2.5 -- 20 mA mA mA mA A A A A VIN = 0 V, VCC See Note 7. VIN = 0 V, VCC See Note 8. VIN = 0 V, VCC WDT is not running VIN = 0 V, VCC WDT is running Measured at 1.3 V -- -- -- -- ICC2 Standby Current4 (STOP mode) 1.9 3.6 1.9 3.6 ILV VBO VLVD VHVD Standby Current5 (Low Voltage) Vcc Low Voltage Protection Vcc Low Voltage Detection Vcc High Voltage Detection -- -- -- -- 1.9-3.6 A V V V TONIRAMP Wake-up time from disabled mode s 19-4572; Rev 0; 4/09 DC Characteristics ZLF645 Series Flash MCUs Product Specification 167 Table 80. DC Characteristics (Continued) TA = 0 C to +70 C Symbol Parameter VCC Min Typ Max Units Conditions IDETLO IR amp current input guaranteed to be detected as a 0 (see Note 6) IR amp current input guaranteed to be detected as a 1 (see Note 6) 1.9-3.6 -- -- 10 A IR amp enabled IDETHI 1.9-3.6 100 -- -- A IR amp enabled Notes 1. Maxim(R) recommends adding a filter capacitor (minimum 0.1 F), physically close to VDD and VSS if operating voltage fluctuations are anticipated, such as those resulting from driving an infrared LED. 2. All outputs unloaded, inputs at rail. 3. CL1 = CL2 = 100 pF. 4. Oscillator stopped. 5. Oscillator stops when VDD falls below VBO limit. 6. For reference, under typical process, 25 C temperature, and a voltage of 2.8 V, the voltage that would be seen at P31 under an input current of 10 uA or 100 uA would be ~480 mV or .560 mV, respectively. 7. 8.0-MHz XTAL1 input clock frequency with 4-MHz system clock 8. 8.0-MHz XTAL1 input clock frequency with 8-MHz system clock 19-4572; Rev 0; 4/09 DC Characteristics ZLF645 Series Flash MCUs Product Specification 168 AC Characteristics Figure 49 and Table 81 lists the alternating current (AC) characteristics of ZLF645 Flash MCU. 1 3 Clock 2 7 7 2 3 T IN 4 6 5 IRQ N 8 9 Clock Setup 11 Stop-Mode Recovery Source 10 Figure 49. AC Timing Diagram 19-4572; Rev 0; 4/09 AC Characteristics ZLF645 Series Flash MCUs Product Specification 169 Table 81. Clock, Reset, Timers, and SMR Timing TA = 0 C to +70 C 8.0 MHz No Symbol Parameter VCC Min Max Units WDTMR (Bits 6, 5, 4, 1, 0) 1 2 3 4 5 6 7 8 9 10 T pC TRC, TFC TWC TWTINL TWTINH TPTIN TRTIN, TFTIN TWIL TWIH TWSM Input Clock Period1 Clock Input Rise and Fall Times1 Input Clock Width1 Timer Input Low Width1 Timer Input High Width1 Timer Input Period1 Timer Input Rise and Fall Timers1 Interrupt Request Low Time1,2 1.9-3.6 1.9-3.6 1.9-3.6 1.9 3.6 1.9-3.6 1.9-3.6 1.9-3.6 1.9 3.6 121 -- 37 100 70 3TPC 8TPC -- 100 70 5TPC 123 10 TPC4 DC 25 -- -- -- -- -- 100 -- -- -- -- ns ns ns ns ns -- -- ns ns ns -- ns -- -- -- -- -- -- -- -- -- -- -- -- Interrupt Request Input 1.9-3.6 High Time1,2 Stop Mode Recovery Width Spec Oscillator Startup Time4 Watchdog Timer Delay Time 1.9-3.6 11 12 TOST TWDT 1.9-3.6 1.9-3.6 1.9-3.6 1.9-3.6 1.9-3.6 1.9-3.6 1.9-3.6 1.9-3.6 -- 5 10 20 80 320 1, 280 5, 120 5TPC -- -- -- -- -- -- -- -- ms ms ms ms ms ms ms -- 0, 0, 0, 0, 0 0, 0, 0, 0, 1 0, 0, 0, 1, 0 0, 0, 0, 1, 1 0, 0, 1, X, X 0, 1, 0, X, X 1, 0, 0, X, X 19-4572; Rev 0; 4/09 AC Characteristics ZLF645 Series Flash MCUs Product Specification 170 Table 81. Clock, Reset, Timers, and SMR Timing (Continued) TA = 0 C to +70 C 8.0 MHz No Symbol Parameter VCC Min Max Units WDTMR (Bits 6, 5, 4, 1, 0) 13 14 TPOR firamp Power-on reset Frequency of input signal for IR amplifier 1.9-3.6 -- 2.5 0 105 500 ms kHz -- -- Notes 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33:P31). 3. SMR - bit 5 = 1. 4. SMR - bit 5 = 0. 5. If bit 1 of the SMR register is programmed to 1, this value is 2.5 ms as measured from the time the oscillator input to XTAL1 reaches a peak to peak voltage oscillation of at least 300 mV. Table 82. Flash Memory Electrical Characteristics and Timing TA = 0 C to +70 C 8.0 MHz No Symbol Parameter Min Max Units Condition 1 2 3 IFLP IFLE IRD Flash Memory Programming Current Flash Memory Page/Mass Erase Current Flash Dynamic Read Current -- -- -- 10 6 420 mA mA a -- -- Assumes reads every clock cycle with a 1 MHz clock -- -- -- -- -- Temp=25 C -- 4 5 6 7 8 9 10 VFLPE VFLR TPROG Tpe Tme Tdr Fen Flash Memory Program/ Erase Voltage Flash Memory Read Voltage Flash Programming Time Flash Page Erase Time Flash Mass Erase Time Flash Data Retention Time Flash Program/Erase Endurance 2.3 1.8 30 10 10 10 20,000 3.6 3.6 60 -- -- -- -- V V us ms ms years cycles 19-4572; Rev 0; 4/09 AC Characteristics ZLF645 Series Flash MCUs Product Specification 171 Flash Option Bits Programmable Flash Option Bits allow user configuration of certain aspects of ZLF645 MCU functionality. This configuration data is stored in the Flash memory Information Block and then read into option byte shadow registers during the last portion of the ZLF645 MCUs reset period. Features available for control through the Flash Option Bits include: * * * * * * * * * * * * Port 0 low nibble pull-ups Port 0 high nibble pull-ups Port 1 low nibble pull-ups Port 1 high nibble pull-ups Port 2 pull-ups Port 3 low nibble pull-ups Port 4 pull-ups WDT always enabled Flash protect entire main memory Flash protect lower half main memory XTAL1 to System Clock (no division enable) 16-bit Stack addressiblity enable Operation Option Bit Shadow Register Loading By Reset For each Flash memory option bit, there is an associated option bit shadow register that is used to register the value of the option bit. The output of the option bit shadow registers are used by the ZLF645 MCU to enable various features and functions for the ZLF645 MCU. Each time the Flash Memory Information Block Option Bits are programmed or erased, the device must be reset for the change in ZLF645 configuration to take effect. A POR or Stop Mode Recovery Reset with SMR bit 5 set to 1, loads the option bits from the Flash memory to the Option Bit Shadow registers during the last few clock cycles of the reset period. In some cases, in order to provide a required value before being loaded, the Option Bit Shadow registers are reset to a predefined value on the start of the reset period. 19-4572; Rev 0; 4/09 Flash Option Bits ZLF645 Series Flash MCUs Product Specification 172 The Option Bit Shadow registers are part of the ZLF645's Register File and are accessible for read/write access. User Option Bit Locations in Flash Memory The user option bits are located in the upper two bytes of the Information block, address FFh and FEh. User Option Bit Shadow Register Access Except for bits 0 and 1 of the User Option Byte 1 Shadow register, the CPU has full read/write access to all the User Option Byte Shadow registers at the address locations given in register tables for each register. User Option Byte 0 and Option Byte 0 Shadow Register Definitions This option byte allows user control over the enabling of the ZLF645's I/O pull-ups and the conditions under which the devices watchdog timer is enabled. For its associated shadow registers, until the registers are loaded with their corresponding option bit values, their outputs will be in an unknown state. Table 83. User Option Byte 0 (OPT0) Bit Field Erased State Flash Address Bit Position Value 7 6 5 4 3 2 1 0 WDT 1 P4PU 1 P3PU 1 P2PU 1 P1HPU 1 P1LPU 1 P0HPU 1 P0LPU 1 Flash Memory Information Area address: FEH Description WDT--Watchdog Timer Enable WDT = 1: WDT is enabled by WDT instruction only. WDT = 0: WDT is always enabled. P4PU through P0LPU--GPIO Pin Pull-Up Enables P4PU = 1: Port 4 Pull-ups disabled. P4PU = 0: Port 4 Pull-ups enabled. P3PU = 1: Port 3 Pull-ups disabled. P3PU = 0: Port 3 Pull-ups enabled. [7] 1 0 [6:0] 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 173 P2PU = 1: Port 2 Pull-ups disabled. P2PU = 0: Port 2 Pull-ups enabled. P1HPU = 1: Port 1 high nibble Pull-ups disabled P1HPU = 0: Port 1 high nibble Pull-ups enabled. P1LPU = 1: Port 1 low nibble Pull-ups disabled. P1LPU = 0: Port 1 low nibble Pull-ups enabled. P0HPU = 1: Port 0 high nibble Pull-ups disabled. P0HPU = 0: Port 0 high nibble Pull-ups enabled. P0LPU = 1: Port 0 low nibble Pull-ups disabled. P0LPU = 0: Port 0 low nibble Pull-ups enabled. Table 84. User Option Byte 0 Shadow Register (OPT0SR) Bit Field Reset State CPU Access (R/W) Register Address (R/W) 7 6 5 4 3 2 1 0 WDT X R/W P4PU X R/W P3PU X R/W P2PU X R/W P1HPU X R/W P1LPU X R/W P0HPU X R/W P0LPU X R/W Bank D: 0Eh; Linear: D0Eh User Option Byte 1 and Option Byte 1 Shadow Register Definitions User Option byte allows the enabling of various features including protecting the Flash's main memory from read operations through either of the ZLF645's Flash access interfaces. For it's associated shadow registers, until the registers are loaded with their corresponding option bit values, their outputs will be in an unknown state. Table 85 describes User Option byte 1 function. Note: This byte can be programmed and erased (by Page 3 erase) only through the ICP. During device Power-on Reset, bit 1 and bit 0 value of this Flash Option byte are sampled into flip-flops, whose outputs control the Flash memory protect function. User codes can read the flip-flop values, by reading from a uniquely assigned peripheral register address. Note: User codes cannot over-write the flip-flop values to change this Flash memory protect function. 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 174 Table 85. User Option Byte 1 (OPT1) Bit Field Erased State Flash Address Bit Position Value 7 6 5 4 3 2 1 0 Reserved 1 1 1 1 16BITSTK DIVBY1 FLPROT1 1 1 1 FLRWP 1 Flash Memory Information Area address: FFH Description Reserved--Must be written 1. 16BITSTK--16 bit Stack Pointer Addressiblity Enable [7:4] [3] -- 1 0 [2] 1 0 [1] 1 The ZLF645 is enabled for 8-bits of stack pointer addressiblity allowing usage of Bank 0 only of the devices general-purpose RAM space as the CPU stack. The ZLF645 is enabled for 16-bits of stack pointer addressiblity allowing usage of all of the devices general-purpose RAM space as the CPU stack. DIVBY1--System Clock Divide By 1 Enable If SMR register bit 0 is also programmed to 0, the system clock frequency is equal to the external clock frequency input on the XTAL1 pin divided by 2. If SMR register bit 0 is also programmed to 0, the system clock frequency is equal to the external clock frequency input on the XTAL1 pin. FLPROT1--Flash Main Memory Lower Half Protect The Flash main memory and all of Information Area Page 3 can be read, written, and erased by both the Flash Byte Programming interface or through the ICP interface as long as FLRWP is also 1. Reads and Writes to the lower half of Flash main memory and writes and erasures to Information Area Page 3, by the ICP or Flash Byte Programming interfaces is disabled unless, with this bit 0, a main memory mass erase is completed first. A main memory mass erase causes resetting of this bit value in the Option Byte 1 shadow register to a 1 but does not effect the corresponding Flash memory bit. Once the Option Byte 1 shadow register bit is reset, the ICP or Flash Byte Programming interface is allowed full read, write, and erase access to the Flash's main memory and to Page 3 of the Information Area and can reset the corresponding Flash memory bit. 0 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 175 [0] 1 FLRWP--Flash Main Memory Protect Flash Main Memory and Information Area Page 3 can be read, programmed, and erased by both the Flash Byte Programming interface or through the ICP interface. Reads and writes to the Flash main memory and writes and erasures to Information Area Page 3 by the ICP or Flash Byte Programming interfaces is disabled unless, with this bit 0, a main memory mass erase is completed first. A main memory mass erase causes resetting of this bit value in the Option Byte 1 shadow register to a 1 but does not effect the corresponding Flash memory bit. Once the Option Byte 1 shadow register bit is reset, the ICP or Flash Byte Programming interface is allowed full read, write, and erase access to the Flash's main memory and to Page 3 of the Information Area and can reset the corresponding Flash memory bit. 0 Table 86. User Option Byte 1 Shadow Register (OPT1SR) Bit Field Reset State CPU Access (R/W) Register Address (R/W) 7 6 5 4 3 2 1 0 RESERVED X X X X 16BITSTK DIVBY1 FLPROT1 FLRWP X R/W 1 R/W X R X R Bank D: 0Fh; Linear: D0Fh Note: RESERVED bits when read by the CPU will return 0 and when written have no effect. 19-4572; Rev 0; 4/09 Operation ZLF645 Series Flash MCUs Product Specification 176 Packaging Figure 50 displays the 20-pin quad flat no-lead (QFN) package for the ZLF645 Series of Flash MCUs. Figure 50. 20-Pin QFN Package Diagram 19-4572; Rev 0; 4/09 Packaging ZLF645 Series Flash MCUs Product Specification 177 Figure 51 displays the 20-pin shrink small outline package (SSOP) for the ZLF645 Series of Flash MCUs. Figure 51. 20-Pin SSOP Package Diagram 19-4572; Rev 0; 4/09 Packaging ZLF645 Series Flash MCUs Product Specification 178 Figure 52 displays the 20-pin small outline integrated circuit (SOIC) package for the ZLF645 Series of Flash MCUs. Figure 52. 20-Pin SOIC Package Diagram 19-4572; Rev 0; 4/09 Packaging ZLF645 Series Flash MCUs Product Specification 179 Figure 53 displays the 20-pin plastic dual inline package (PDIP) for the ZLF645 Series of Flash MCUs. Figure 53. 20-Pin PDIP Package Diagram 19-4572; Rev 0; 4/09 Packaging ZLF645 Series Flash MCUs Product Specification 180 Figure 54 displays the 28-pin shrink small outline package (SSOP) for the ZLF645 Series of Flash MCUs. D 28 15 C SYMBOL A E H A1 A2 B C 1 14 DETAIL A D E e Q1 H L A2 7.65 0.63 MIN 1.73 0.05 1.68 0.25 0.09 10.07 5.20 10.20 5.30 0.65 TYP 7.80 0.75 7.90 0.95 0.301 0.025 MILLIMETER NOM 1.86 0.13 1.73 MAX 1.99 0.21 1.78 0.38 0.20 10.33 5.38 MIN 0.068 0.002 0.066 0.010 0.004 0.397 0.205 0.006 0.402 0.209 0.0256 TYP 0.307 0.030 0.311 0.037 INCH NOM 0.073 0.005 0.068 MAX 0.078 0.008 0.070 0.015 0.008 0.407 0.212 A1 A e B SEATING PLANE CONTROLLING DIMENSIONS: MM LEADS ARE COPLANAR WITHIN .004 INCHES. L 0-8 DETAIL 'A' Figure 54. 28-Pin SSOP Package Diagram 19-4572; Rev 0; 4/09 Packaging ZLF645 Series Flash MCUs Product Specification 181 Figure 55 displays the 28-pin small outline integrated circuit (SOIC) package for the ZLF645 Series of Flash MCUs. Figure 55. 28-Pin SOIC Package Diagram 19-4572; Rev 0; 4/09 Packaging ZLF645 Series Flash MCUs Product Specification 182 Figure 56 displays the 28-pin plastic dual inline package (PDIP) for the ZLF645 Series of Flash MCUs. Z log Figure 56. 28-Pin PDIP Package Diagram 19-4572; Rev 0; 4/09 Packaging ZLF645 Series Flash MCUs Product Specification 183 Figure 57 displays the 48-pin shrink small outline package (SSOP) for the ZLF645 Series of Flash MCUs. 20984 05-07-07 M. Fonte Figure 57. 48-Pin SSOP Package Diagram 19-4572; Rev 0; 4/09 Packaging ZLF645 Series Flash MCUs Product Specification 184 Ordering Information Table 87 lists the part numbers for ZLF645 Series of Flash MCUs and a brief description of each part. Table 87. ZLF645 Flash MCU Part Numbers Description Part Number Flash (KB) RAM Description ZLF645 Flash MCU with 512 B RAM ZLF645S0H2064G ZLF645S0H2864G ZLF645S0H4864G ZLF645S0P2064G ZLF645S0P2864G ZLF645S0S2064G ZLF645S0S2864G ZLF645S0Q2064G ZLF645S0H2032G ZLF645S0H2832G ZLF645S0H4832G ZLF645S0P2032G ZLF645S0P2832G ZLF645S0S2032G ZLF645S0S2832G ZLF645S0Q2032G ZLF645E0H2064G ZLF645E0H2864G ZLF645E0H4864G ZLF645E0P2064G ZLF645E0P2864G ZLF645E0S2064G ZLF645E0S2864G 64 64 64 64 64 64 64 64 32 32 32 32 32 32 32 32 64 64 64 64 64 64 64 512 B 512 B 512 B 512 B 512 B 512 B 512 B 512 B 512 B 512 B 512 B 512 B 512 B 512 B 512 B 512B 1K 1K 1K 1K 1K 1K 1K SSOP 20-pin package SSOP 28-pin package SSOP 48-pin package PDIP 20-pin package PDIP 28-pin package SOIC 20-pin package SOIC 28-pin package QFN 20-pin package SSOP 20-pin package SSOP 28-pin package SSOP 48-pin package PDIP 20-pin package PDIP 28-pin package SOIC 20-pin package SOIC 28-pin package QFN 20-pin package SSOP 20-pin package SSOP 28-pin package SSOP 48-pin package PDIP 20-pin package PDIP 28-pin package SOIC 20-pin package SOIC 28-pin package ZLF645 Flash MCU with 1K RAM 19-4572; Rev 0; 4/09 Ordering Information ZLF645 Series Flash MCUs Product Specification 185 Table 87. ZLF645 Flash MCU Part Numbers Description (Continued) Part Number Flash (KB) RAM Description ZLF645E0Q2064G ZLF645E0H2032G ZLF645E0H2832G ZLF645E0H4832G ZLF645E0P2032G ZLF645E0P2832G ZLF645E0S2032G ZLF645E0S2832G ZLF645E0Q2032G ZCRMZNICE01ZEMG 64 32 32 32 32 32 32 32 32 1K 1K 1K 1K 1K 1K 1K 1K 1K QFN 20-pin package SSOP 20-pin package SSOP 28-pin package SSOP 48-pin package PDIP 20-pin package PDIP 28-pin package SOIC 20-pin package SOIC 28-pin package QFN 20-pin package Crimzon ICE Kit (includes Smart Cable for ZLF645 in-circuit programming) Crimzon/ZLF645 IR Development Board Kit Crimzon/ZLF645 20-Pin Accessory Kit Crimzon/ZLF645 40-/48-Pin Accessory Kit ZCRMZN00100KITG ZCRMZNICE01ZACG ZCRMZNICE02ZACG 19-4572; Rev 0; 4/09 Ordering Information ZLF645 Series Flash MCUs Product Specification 186 Part Number Description Maxim(R) part numbers consist of a number of components as shown below: Z L F 645 E0 H 48 64 G Environmental Flow G = Lead Free (Green part) Flash Memory 64 = 64 KB 32 = 32 KB Number of Pins in Package 48 = 48-Pin 28 = 28-Pin 20 = 20-Pin Package Type H = SSOP P = PDIP S = SOIC Q = QFN RAM Size E0 = Extended 1K RAM S0 = Standard 512 B RAM Family Series Memory Type F = Flash Low Voltage Maxim Index 19-4572; Rev 0; 4/09 Part Number Description ZLF645 Series Flash MCUs Product Specification 187 Index Numerics 11890 Figure Title 12-bit address map 47 16-bit counter/timer circuits 109 20-pin package pins 6, 8, 9 PDIP package 179, 183 SOIC package 178 SSOP package 177 28-pin package pins 11, 13, 16 PDIP package 182 SOIC package 181 SSOP package 176, 180 32178 Figure Title active low notation 3 address 12-bit linear 47 notation 157 amplifier, infrared 84 AND caution 119 architecture UART 86 asynchronous data 87 Figure 34. Resets and WDT 138 B baud rate generator description 93 example 94 interrupt 93 Baud Rate Generator Constant register (BCNST) 97, 98 block diagram counter/timer 99 interrupt 128 MCU 4 reset and watch-dog timer 138 UART 86 brown-out, voltage 143 brownout, voltage 139 Figure 17. T8_OUT in MODULO-N Mode 104 40203 Figure Title Figure 16. T8_OUT in SINGLE-PASS Mode 104 60053 Table Title Table 32. Stop Mode Recovery Register 2 155 64329 Table Title C capacitance 164 caution stopping timer 104 timer count 103 timer modes 121 timer registers 110 UART transmit 88, 89 characteristics AC 168, 169 DC 165 clock 134 8-bit counter/timer circuits 103 Table 37. Stop Mode Recovery Register 4 156 A absolute maximum ratings 163 AC characteristics 168, 169 AC timing 168 19-4572; Rev 0; 4/09 Index ZLF645 Series Flash MCUs Product Specification 188 internal signals 135 comparator inputs 28 outputs 28 condition codes 161 conditions, test 164 connection, power 3 constant memory 41 constant, baud rate 97, 98 counter/timer block diagram 99 capture flowchart 106 input circuit 101 output configuration 27 crystal 134 crystal oscillator pins (XTAL1, XTAL2) 134, 135 Customer Support 193 F fast recovery, stop mode 143 features, device 1 flags register 160 flash option bit configuration - reset 171 flash memory 67, 82 arrrangement 68 byte programming 74 code protection 73 configurations 67 control register definitions 75 flash status register 77 flow chart 72 frequency high and low byte registers 79 mass erase 75 operation 69 operation timing 69 page erase 74 page select register 77, 78 flowchart demodulation mode 106, 107, 108 timer transmit 102 UART receive 92 format, UART data 87 FPS register 77, 78 FSTAT register 77 functional block diagram 4 D data format, UART 87 data handling, UART 91 DC characteristics 165 demodulation changing mode 121 flowchart 106, 107 timer 105, 110 demodulation mode flowchart 108 device block diagram 4 features 1 diagram, package 176, 177, 178, 179, 180, 181, 182, 183 divisor, baud rate 97, 98 H h suffix 104 HALT mode 143 handshaking, UART 90 E electrical characteristics 163 error handling, UART 91 example BCNST register 94 register pointer 45 I ICP architecture 54 auto-baud detector/generator 55 baud rate limits 56 block diagram 54 commands 57 19-4572; Rev 0; 4/09 Index ZLF645 Series Flash MCUs Product Specification 189 control register 64 data format 55 debug mode 54 serial errors 56 status register 65 ICP commands read ICP control register (05H) 59 read ICP revision (00H) 58 read ICP status register (02H) 59 read program memory (0BH) 60 read program memory CRC (0EH) 60 read register (09H) 59 read runtime counter (03H) 59 write ICP control register (04H) 59 write program memory (0AH) 59, 61 write register (08H) 59 ICP Interface 53 infrared learning amplifier 84 input comparator 28 counter/timer 101 timers 100 instruction set summary 162 instruction symbols 159 internal clock 135 interrupt baud rate generator 93 block diagram 128 description 127 mask register 133 priority register 130 request register 130, 131 source 129 stop-mode recovery 144 type 129 UART 90 UART receive 89, 90, 92 UART transmit 88, 90 vector 129 Interrupt Mask Register (IMR) 133 Interrupt Priority Register (IPR) 130 Interrupt Request Register (IRQ) 130, 131 L LDE and LDEI instructions removed 46 LDX, LDXI instruction addresses 47 learning amplifier, infrared 84 linear address 45 load, test 164 Low-Voltage Detection Register (LVD) 140 M map program/constant memory 41 register 12-bit 47 register 8-bit 43 register file summary 50 maximum ratings 163 MCU block diagram 4 features 1 memory address, linear 45 program/constant map 41 register 12-bit map 47 register file map 43 register file summary 50 modulo-N mode 104, 110 N notation addressing 157 operand 157 O operand symbols 157 operation, UART 86 Operational Description 67, 171 OR caution 119 oscillator 134 output comparator 28 timer/counter 112 19-4572; Rev 0; 4/09 Index ZLF645 Series Flash MCUs Product Specification 190 timer/counter circuit 113 timer/counter configuration 27 overline, in text 3 overrun, UART 91 program memory map 41 programming summary 157 R P package diagram 176, 177, 178, 179, 180, 181, 182, 183 package information 176 parity, UART data 87 pin description 5 pin function port 0 20 port 2 21, 28 port 3 23 port 3 summary 26 ping-pong mode 111, 112 pins 20-pin package 6, 8, 9 28-pin package 11, 13, 16 polled UART receive 89 polled UART transmit 87 port 0 configuration 20 pin function 20 Port 0 Mode Register (P01M) 31 Port 0 Register (P0) 32 port 2 configuration 22 pin function 21, 28 Port 2 Mode Register (P2M) 34, 39 Port 2 Register (P2) 33, 35, 40 port 3 configuration 24 counter/timer output 27 pin function 23 pin function 26 Port 3 Mode Register (P3M) 36 Port 3 Register (P3) 37 Port Configuration Register (PCON) 28, 30 power connection 3 power management 137 power-on reset timer 139 ratings, maximum 163 register BCNST 98 CTR1 121 CTR3 126 flash high and low byte (FFREQH and FREEQL) 79 flash page select (FPS) 77, 78 flash status (FSTAT) 77 HI16 115 HI8 114 ICP control 64 ICP status 65 IMR 133 IPR 130 IRQ 130, 131 LO16 116 LO8 115 LVD 140 P0 32 P01M 31 P2 33, 35, 40 P2M 34, 39 P3 37 P3M 36 PCON 28, 30 Register Pointer register 48 RP 48 SMR 146 SMR1 150 SMR2 152 SMR3 155 SMR4 156 SPL 48, 49 UCTL 96, 97 URDATA 95 USER 48 UST 95 19-4572; Rev 0; 4/09 Index ZLF645 Series Flash MCUs Product Specification 191 UTDATA 95 WDTMR 142 register file 12-bit address 47 address summary 50 description 42 memory map 43 register pointer detail 44 example 45 Register Pointer Register 48 Register Pointer Register (RP) 48 Register Pointer register (RP) 48 reset block diagram 138 delay bypass 143 features 137 POR timer 139 status 143 timer terminal count 119 Stop Mode Recovery Register 4 (SMR4) 156 stop-mode description 143 recovery events 144, 147, 150, 152 recovery interrupt 144 recovery source 144, 145, 149, 151 recovery status 143 Stop-Mode Recovery Register 4 (SMR4) 156 suffix, h 104 symbols address 157 instruction 159 operand 157 T T16_OUT signal modulo-N mode 110 T8_OUT signal modulo-N mode 104 single-pass mode 104 TCLK signal 135 terminal count, reset 119 test conditions 164 test load 164 timer block diagram 99 changing mode 121 description 99 input circuit 100, 101 output circuit 113 output configuration 27 output description 112 reset 139 starting count caution 103 stopping caution 104 T16 demodulation 110 T16 transmit 109 T16_OUT signal 110 T8 demodulation 105 T8 transmit 101 T8_OUT signal 104 transmit flowchart 102 transmit versus demodulation mode 121 S SCLK signal 135 single-pass mode 104 source interrupt 129 stop mode recovery 144 stop-mode recovery 145, 149, 151 stack 42 Stack Pointer Register (SPL) 48, 49 standard test conditions 164 standby, brown-out 139 standby, brownout 143 status reset 143 UART 95 stop bit, UART 91 stop mode fast recovery 143 Stop Mode Recovery Register (SMR) 146 Stop Mode Recovery Register 1 (SMR1) 150 Stop Mode Recovery Register 2 (SMR2) 152 Stop Mode Recovery Register 3 (SMR3) 155 19-4572; Rev 0; 4/09 Index ZLF645 Series Flash MCUs Product Specification 192 Timer 16 Capture High Register (HI16) 115 Timer 16 Capture Low Register (L016) 116 Timer 16 Control register (CTR2) 124 Timer 16 High Hold register (TC16H) 116 Timer 16 Low Hold Register (TC16L) 117 Timer 8 and Timer 16 Common Functions Register (CTR1) 121 Timer 8 Capture High Register (HI8) 114 Timer 8 Capture Low Register (L08) 115 Timer 8 Control Register (CTR0) 119 Timer 8 High Hold Register (TC8H) 117 Timer 8 Low Hold Register (TC8L) 118 Timer 8/Timer 16 Control Register (CTR3) 126 timing, AC 168 transmit caution, UART 88, 89 transmit mode caution 121 flowchart 102 timer 101, 109 V vector, interrupt 129 voltage brown-out 139, 143 detection 143 detection register 140 W Watchdog Timer description 141 watchdog timer diagram 138 Watchdog Timer Mode Register (WDTMR) 142 X XTAL1 pin 134 XTAL2 pin 135 U UART architecture 86 baud rate generator 93 block diagram 86 data and error handling 91 data format 87 interrupts 90 operation 86 overrun error 91 polled receive 89 polled transmit 87 receive interrupt 89, 90, 92 stop bit 91 transmit caution 88, 89 transmit interrupt 88, 90 UART Control Register (UCTL) 96, 97 UART Receive/Transmit Data Register (URDATA/UTDATA) 95 UART Status Register (UST) 95 User Data Register (USER) 48 Z ZLR64400 MCU block diagram 4 features 1 19-4572; Rev 0; 4/09 Index ZLF645 Series Flash MCUs Product Specification 193 Customer Support For any comments, detail technical questions, or reporting problems, please visit Maxim's Technical Support at https://support.maxim-ic.com/micro. 19-4572; Rev 0; 4/09 Customer Support |
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